dmaengine: edma: Create private pset struct
Preparatory patch to support finer grained accounting. Move the edma_params array out of edma_desc so we can add further per pset data to it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> [joelf@ti.com: Fixed up hunk #3 in original patch to apply] Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Thomas Gleixner
Vinod Koul
parent
de13593971
commit
b5088ad963
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@ -57,6 +57,10 @@
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#define EDMA_MAX_SLOTS MAX_NR_SG
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#define EDMA_DESCRIPTORS 16
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struct edma_pset {
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struct edmacc_param param;
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};
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struct edma_desc {
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struct virt_dma_desc vdesc;
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struct list_head node;
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@ -65,7 +69,7 @@ struct edma_desc {
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int pset_nr;
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int processed;
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u32 residue;
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struct edmacc_param pset[0];
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struct edma_pset pset[0];
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};
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struct edma_cc;
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@ -141,7 +145,7 @@ static void edma_execute(struct edma_chan *echan)
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/* Write descriptor PaRAM set(s) */
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for (i = 0; i < nslots; i++) {
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j = i + edesc->processed;
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edma_write_slot(echan->slot[i], &edesc->pset[j]);
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edma_write_slot(echan->slot[i], &edesc->pset[j].param);
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dev_vdbg(echan->vchan.chan.device->dev,
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"\n pset[%d]:\n"
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" chnum\t%d\n"
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@ -155,14 +159,14 @@ static void edma_execute(struct edma_chan *echan)
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" cidx\t%08x\n"
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" lkrld\t%08x\n",
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j, echan->ch_num, echan->slot[i],
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edesc->pset[j].opt,
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edesc->pset[j].src,
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edesc->pset[j].dst,
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edesc->pset[j].a_b_cnt,
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edesc->pset[j].ccnt,
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edesc->pset[j].src_dst_bidx,
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edesc->pset[j].src_dst_cidx,
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edesc->pset[j].link_bcntrld);
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edesc->pset[j].param.opt,
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edesc->pset[j].param.src,
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edesc->pset[j].param.dst,
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edesc->pset[j].param.a_b_cnt,
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edesc->pset[j].param.ccnt,
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edesc->pset[j].param.src_dst_bidx,
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edesc->pset[j].param.src_dst_cidx,
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edesc->pset[j].param.link_bcntrld);
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/* Link to the previous slot if not the last set */
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if (i != (nslots - 1))
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edma_link(echan->slot[i], echan->slot[i+1]);
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@ -305,13 +309,14 @@ static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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* @dma_length: Total length of the DMA transfer
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* @direction: Direction of the transfer
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*/
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static int edma_config_pset(struct dma_chan *chan, struct edmacc_param *pset,
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static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset,
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dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
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enum dma_slave_buswidth dev_width, unsigned int dma_length,
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enum dma_transfer_direction direction)
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{
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struct edma_chan *echan = to_edma_chan(chan);
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struct device *dev = chan->device->dev;
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struct edmacc_param *param = &epset->param;
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int acnt, bcnt, ccnt, cidx;
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int src_bidx, dst_bidx, src_cidx, dst_cidx;
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int absync;
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@ -391,26 +396,26 @@ static int edma_config_pset(struct dma_chan *chan, struct edmacc_param *pset,
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return -EINVAL;
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}
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pset->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
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param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
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/* Configure A or AB synchronized transfers */
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if (absync)
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pset->opt |= SYNCDIM;
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param->opt |= SYNCDIM;
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pset->src = src_addr;
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pset->dst = dst_addr;
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param->src = src_addr;
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param->dst = dst_addr;
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pset->src_dst_bidx = (dst_bidx << 16) | src_bidx;
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pset->src_dst_cidx = (dst_cidx << 16) | src_cidx;
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param->src_dst_bidx = (dst_bidx << 16) | src_bidx;
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param->src_dst_cidx = (dst_cidx << 16) | src_cidx;
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pset->a_b_cnt = bcnt << 16 | acnt;
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pset->ccnt = ccnt;
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param->a_b_cnt = bcnt << 16 | acnt;
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param->ccnt = ccnt;
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/*
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* Only time when (bcntrld) auto reload is required is for
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* A-sync case, and in this case, a requirement of reload value
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* of SZ_64K-1 only is assured. 'link' is initially set to NULL
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* and then later will be populated by edma_execute.
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*/
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pset->link_bcntrld = 0xffffffff;
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param->link_bcntrld = 0xffffffff;
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return absync;
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}
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@ -498,11 +503,11 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
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/* If this is the last in a current SG set of transactions,
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enable interrupts so that next set is processed */
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if (!((i+1) % MAX_NR_SG))
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edesc->pset[i].opt |= TCINTEN;
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edesc->pset[i].param.opt |= TCINTEN;
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/* If this is the last set, enable completion interrupt flag */
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if (i == sg_len - 1)
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edesc->pset[i].opt |= TCINTEN;
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edesc->pset[i].param.opt |= TCINTEN;
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}
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return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
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@ -661,14 +666,14 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
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" cidx\t%08x\n"
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" lkrld\t%08x\n",
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i, echan->ch_num, echan->slot[i],
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edesc->pset[i].opt,
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edesc->pset[i].src,
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edesc->pset[i].dst,
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edesc->pset[i].a_b_cnt,
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edesc->pset[i].ccnt,
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edesc->pset[i].src_dst_bidx,
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edesc->pset[i].src_dst_cidx,
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edesc->pset[i].link_bcntrld);
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edesc->pset[i].param.opt,
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edesc->pset[i].param.src,
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edesc->pset[i].param.dst,
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edesc->pset[i].param.a_b_cnt,
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edesc->pset[i].param.ccnt,
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edesc->pset[i].param.src_dst_bidx,
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edesc->pset[i].param.src_dst_cidx,
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edesc->pset[i].param.link_bcntrld);
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edesc->absync = ret;
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@ -676,7 +681,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
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* Enable interrupts for every period because callback
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* has to be called for every period.
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*/
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edesc->pset[i].opt |= TCINTEN;
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edesc->pset[i].param.opt |= TCINTEN;
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}
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return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
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