staging: ccree: remove descriptor context definitions
Remove definitions of descriptor context which are not used in the driver. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -196,91 +196,5 @@ enum drv_crypto_padding_type {
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DRV_PADDING_RESERVE32B = S32_MAX
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};
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/*******************************************************************/
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/***************** DESCRIPTOR BASED CONTEXTS ***********************/
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/*******************************************************************/
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/* Generic context ("super-class") */
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struct drv_ctx_generic {
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enum drv_crypto_alg alg;
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} __attribute__((__may_alias__));
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struct drv_ctx_hash {
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enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_HASH */
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enum drv_hash_mode mode;
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u8 digest[CC_DIGEST_SIZE_MAX];
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/* reserve to end of allocated context size */
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u8 reserved[CC_CTX_SIZE - 2 * sizeof(u32) -
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CC_DIGEST_SIZE_MAX];
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};
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/* NOTE! drv_ctx_hmac should have the same structure as drv_ctx_hash except
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* k0, k0_size fields
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*/
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struct drv_ctx_hmac {
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enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_HMAC */
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enum drv_hash_mode mode;
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u8 digest[CC_DIGEST_SIZE_MAX];
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u32 k0[CC_HMAC_BLOCK_SIZE_MAX / sizeof(u32)];
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u32 k0_size;
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/* reserve to end of allocated context size */
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u8 reserved[CC_CTX_SIZE - 3 * sizeof(u32) -
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CC_DIGEST_SIZE_MAX - CC_HMAC_BLOCK_SIZE_MAX];
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};
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struct drv_ctx_cipher {
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enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_AES */
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enum drv_cipher_mode mode;
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enum drv_crypto_direction direction;
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enum drv_crypto_key_type crypto_key_type;
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enum drv_crypto_padding_type padding_type;
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u32 key_size; /* numeric value in bytes */
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u32 data_unit_size; /* required for XTS */
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/* block_state is the AES engine block state.
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* It is used by the host to pass IV or counter at initialization.
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* It is used by SeP for intermediate block chaining state and for
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* returning MAC algorithms results.
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*/
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u8 block_state[CC_AES_BLOCK_SIZE];
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u8 key[CC_AES_KEY_SIZE_MAX];
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u8 xex_key[CC_AES_KEY_SIZE_MAX];
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/* reserve to end of allocated context size */
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u32 reserved[CC_DRV_CTX_SIZE_WORDS - 7 -
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CC_AES_BLOCK_SIZE / sizeof(u32) - 2 *
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(CC_AES_KEY_SIZE_MAX / sizeof(u32))];
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};
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/* authentication and encryption with associated data class */
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struct drv_ctx_aead {
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enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_AES */
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enum drv_cipher_mode mode;
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enum drv_crypto_direction direction;
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u32 key_size; /* numeric value in bytes */
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u32 nonce_size; /* nonce size (octets) */
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u32 header_size; /* finit additional data size (octets) */
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u32 text_size; /* finit text data size (octets) */
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u32 tag_size; /* mac size, element of {4, 6, 8, 10, 12, 14, 16} */
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/* block_state1/2 is the AES engine block state */
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u8 block_state[CC_AES_BLOCK_SIZE];
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u8 mac_state[CC_AES_BLOCK_SIZE]; /* MAC result */
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u8 nonce[CC_AES_BLOCK_SIZE]; /* nonce buffer */
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u8 key[CC_AES_KEY_SIZE_MAX];
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/* reserve to end of allocated context size */
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u32 reserved[CC_DRV_CTX_SIZE_WORDS - 8 -
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3 * (CC_AES_BLOCK_SIZE / sizeof(u32)) -
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CC_AES_KEY_SIZE_MAX / sizeof(u32)];
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};
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/*******************************************************************/
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/***************** MESSAGE BASED CONTEXTS **************************/
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/*******************************************************************/
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/* Get the address of a @member within a given @ctx address
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* @ctx: The context address
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* @type: Type of context structure
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* @member: Associated context field
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*/
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#define GET_CTX_FIELD_ADDR(ctx, type, member) ((ctx) + offsetof(type, member))
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#endif /* _CC_CRYPTO_CTX_H_ */
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