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wlcore/wl12xx/wl18xx: don't use TX align quirk for wl127x 

Commit 4afc37 (wlcore: reorder identify_chip and get_hw_info) broke
support for wl127x chips.

When we moved the identify_chip operation to an earlier stage (ie. to
the probe function), we broke wl127x support because during HW init we
would set the WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN.

To avoid this, set this quirk in the identify_chip operations and only
force it to be unset if the bus module doesn't support it.  We were
doing the opposite and setting the flag if the bus module supports it.

Signed-off-by: Luciano Coelho <coelho@ti.com>
This commit is contained in:
Luciano Coelho 2012-06-05 00:02:25 +03:00
parent 3d62eb5a7e
commit b5d6d9b28c
3 changed files with 12 additions and 10 deletions
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10
drivers/net/wireless/ti/wl12xx/main.c
View File

@ -625,9 +625,6 @@ static int wl12xx_identify_chip(struct wl1271 *wl)
wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
wl->chip.id);
/* clear the alignment quirk, since we don't support it */
wl->quirks &= ~WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
wl->quirks |= WLCORE_QUIRK_LEGACY_NVS;
wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
wl->mr_fw_name = WL127X_FW_NAME_MULTI;
@ -643,9 +640,6 @@ static int wl12xx_identify_chip(struct wl1271 *wl)
wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
wl->chip.id);
/* clear the alignment quirk, since we don't support it */
wl->quirks &= ~WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
wl->quirks |= WLCORE_QUIRK_LEGACY_NVS;
wl->plt_fw_name = WL127X_PLT_FW_NAME;
wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
@ -664,6 +658,10 @@ static int wl12xx_identify_chip(struct wl1271 *wl)
wl->plt_fw_name = WL128X_PLT_FW_NAME;
wl->sr_fw_name = WL128X_FW_NAME_SINGLE;
wl->mr_fw_name = WL128X_FW_NAME_MULTI;
/* wl128x requires TX blocksize alignment */
wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
break;
case CHIP_ID_1283_PG10:
default:

5
drivers/net/wireless/ti/wl18xx/main.c
View File

@ -591,8 +591,9 @@ static int wl18xx_identify_chip(struct wl1271 *wl)
/* wl18xx uses the same firmware for PLT */
wl->plt_fw_name = WL18XX_FW_NAME;
wl->quirks |= WLCORE_QUIRK_NO_ELP |
WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED |
WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN;
WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED |
WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
/* PG 1.0 has some problems with MCS_13, so disable it */
wl->ht_cap.mcs.rx_mask[1] &= ~BIT(5);

7
drivers/net/wireless/ti/wlcore/main.c
View File

@ -960,9 +960,12 @@ static int wl12xx_chip_wakeup(struct wl1271 *wl, bool plt)
* simplify the code and since the performance impact is
* negligible, we use the same block size for all different
* chip types.
*
* Check if the bus supports blocksize alignment and, if it
* doesn't, make sure we don't have the quirk.
*/
if (wl1271_set_block_size(wl))
wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
if (!wl1271_set_block_size(wl))
wl->quirks &= ~WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
/* TODO: make sure the lower driver has set things up correctly */