OpenE2K
/
linux
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

sunxi: Cleanup the reset code and add meaningful registers defines 

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Maxime Ripard 2013-02-04 23:32:39 +01:00 committed by Olof Johansson
parent b28eaacfbb
commit b60decad77
1 changed files with 15 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
arch/arm/mach-sunxi/sunxi.c
View File

@ -27,7 +27,10 @@
#include "sunxi.h" #include "sunxi.h"
#define WATCHDOG_CTRL_REG 0x00 #define WATCHDOG_CTRL_REG 0x00
#define WATCHDOG_CTRL_RESTART (1 << 0)
#define WATCHDOG_MODE_REG 0x04 #define WATCHDOG_MODE_REG 0x04
#define WATCHDOG_MODE_ENABLE (1 << 0)
#define WATCHDOG_MODE_RESET_ENABLE (1 << 1)
static void __iomem *wdt_base; static void __iomem *wdt_base;
@ -48,11 +51,19 @@ static void sunxi_restart(char mode, const char *cmd)
return; return;
/* Enable timer and set reset bit in the watchdog */ /* Enable timer and set reset bit in the watchdog */
writel(3, wdt_base + WATCHDOG_MODE_REG); writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,
writel(0xa57 << 1 | 1, wdt_base + WATCHDOG_CTRL_REG); wdt_base + WATCHDOG_MODE_REG);
while(1) {
/*
* Restart the watchdog. The default (and lowest) interval
* value for the watchdog is 0.5s.
*/
writel(WATCHDOG_CTRL_RESTART, wdt_base + WATCHDOG_CTRL_REG);
while (1) {
mdelay(5); mdelay(5);
writel(3, wdt_base + WATCHDOG_MODE_REG); writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,
wdt_base + WATCHDOG_MODE_REG);
} }
} }