Merge branch 'for-linus' of git://codeaurora.org/quic/kernel/davidb/linux-msm
* 'for-linus' of git://codeaurora.org/quic/kernel/davidb/linux-msm: (35 commits) mmc: msm_sdcc: Check for only DATA_END interrupt to end a request mmc: msm_sdcc: Fix bug in PIO mode when data size is not word aligned mmc: msm_sdcc: Reset SDCC in case of data transfer errors mmc: msm_sdcc: Add prog done interrupt support mmc: msm_sdcc: Fix possible circular locking dependency warning MSM: Add USB support for MSM7x30 MSM: Add USB suport for QSD8x50 msm: initial framebuffer support msm: add handling for clocks tagged as CLK_MINMAX msm: trout: change name of pmdh_clk to mddi_clk msm: add CLK_MINMAX to pmdh_clk msm: trout: add gpio_to_irq msm: iommu: Use the correct memory allocation flag msm_serial: Remove redundant unlikely() msm: iommu: Miscellaneous code cleanup msm: iommu: Support cache-coherent memory access msm: iommu: Definitions for extended memory attributes msm: iommu: Kconfig dependency for the IOMMU API msm: iommu: Check if device is already attached msm: iommu: Kconfig item for cacheable page tables ...
This commit is contained in:
commit
b69fc2efc9
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@ -44,6 +44,7 @@ config ARCH_MSM8X60
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select CPU_V7
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select MSM_V2_TLMM
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select MSM_GPIOMUX
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select IOMMU_API
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endchoice
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@ -122,6 +123,10 @@ config MACH_MSM8X60_FFA
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endmenu
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config IOMMU_PGTABLES_L2
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def_bool y
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depends on ARCH_MSM8X60 && MMU && SMP && CPU_DCACHE_DISABLE=n
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config MSM_DEBUG_UART
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int
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default 1 if MSM_DEBUG_UART1
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@ -162,4 +167,7 @@ config MSM_GPIOMUX
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config MSM_V2_TLMM
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bool
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config IOMMU_API
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bool
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endif
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@ -20,6 +20,7 @@ obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
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obj-$(CONFIG_MSM_SMD) += last_radio_log.o
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obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o
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obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o
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obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
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obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
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obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
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@ -28,6 +29,8 @@ obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
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obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o
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obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
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obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
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ifndef CONFIG_MSM_V2_TLMM
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ifdef CONFIG_MSM_V2_TLMM
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obj-y += gpio-v2.o
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else
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obj-y += gpio.o
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endif
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@ -22,6 +22,7 @@
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/smsc911x.h>
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#include <linux/usb/msm_hsusb.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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@ -39,11 +40,26 @@
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extern struct sys_timer msm_timer;
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static int hsusb_phy_init_seq[] = {
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0x30, 0x32, /* Enable and set Pre-Emphasis Depth to 20% */
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0x02, 0x36, /* Disable CDR Auto Reset feature */
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-1
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};
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static struct msm_otg_platform_data msm_otg_pdata = {
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.phy_init_seq = hsusb_phy_init_seq,
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.mode = USB_PERIPHERAL,
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.otg_control = OTG_PHY_CONTROL,
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};
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static struct platform_device *devices[] __initdata = {
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#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
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&msm_device_uart2,
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#endif
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&msm_device_smd,
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&msm_device_otg,
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&msm_device_hsusb,
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&msm_device_hsusb_host,
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};
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static void __init msm7x30_init_irq(void)
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@ -53,6 +69,10 @@ static void __init msm7x30_init_irq(void)
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static void __init msm7x30_init(void)
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{
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msm_device_otg.dev.platform_data = &msm_otg_pdata;
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msm_device_hsusb.dev.parent = &msm_device_otg.dev;
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msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
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platform_add_devices(devices, ARRAY_SIZE(devices));
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}
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@ -20,6 +20,7 @@
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/usb/msm_hsusb.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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@ -74,9 +75,24 @@ static int __init msm_init_smc91x(void)
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}
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module_init(msm_init_smc91x);
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static int hsusb_phy_init_seq[] = {
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0x08, 0x31, /* Increase HS Driver Amplitude */
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0x20, 0x32, /* Enable and set Pre-Emphasis Depth to 10% */
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-1
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};
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static struct msm_otg_platform_data msm_otg_pdata = {
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.phy_init_seq = hsusb_phy_init_seq,
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.mode = USB_PERIPHERAL,
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.otg_control = OTG_PHY_CONTROL,
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};
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static struct platform_device *devices[] __initdata = {
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&msm_device_uart3,
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&msm_device_smd,
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&msm_device_otg,
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&msm_device_hsusb,
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&msm_device_hsusb_host,
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};
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static void __init qsd8x50_map_io(void)
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@ -93,6 +109,9 @@ static void __init qsd8x50_init_irq(void)
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static void __init qsd8x50_init(void)
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{
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msm_device_otg.dev.platform_data = &msm_otg_pdata;
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msm_device_hsusb.dev.parent = &msm_device_otg.dev;
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msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
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platform_add_devices(devices, ARRAY_SIZE(devices));
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}
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@ -72,6 +72,13 @@ static int msm_gpiolib_direction_output(struct gpio_chip *chip,
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return 0;
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}
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static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
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return TROUT_GPIO_TO_INT(offset + chip->base);
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}
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#define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val) \
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{ \
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.chip = { \
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@ -80,6 +87,7 @@ static int msm_gpiolib_direction_output(struct gpio_chip *chip,
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.direction_output = msm_gpiolib_direction_output, \
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.get = msm_gpiolib_get, \
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.set = msm_gpiolib_set, \
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.to_irq = trout_gpio_to_irq, \
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.base = base_gpio, \
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.ngpio = 8, \
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}, \
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@ -0,0 +1,297 @@
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/* linux/arch/arm/mach-msm/board-trout-mddi.c
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** Author: Brian Swetland <swetland@google.com>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/leds.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/mach-types.h>
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#include <mach/msm_fb.h>
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#include <mach/vreg.h>
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#include "board-trout.h"
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#include "proc_comm.h"
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#include "devices.h"
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#define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255
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#define MDDI_CLIENT_CORE_BASE 0x108000
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#define LCD_CONTROL_BLOCK_BASE 0x110000
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#define SPI_BLOCK_BASE 0x120000
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#define I2C_BLOCK_BASE 0x130000
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#define PWM_BLOCK_BASE 0x140000
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#define GPIO_BLOCK_BASE 0x150000
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#define SYSTEM_BLOCK1_BASE 0x160000
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#define SYSTEM_BLOCK2_BASE 0x170000
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#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
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#define SYSCLKENA (MDDI_CLIENT_CORE_BASE|0x2C)
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#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
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#define V_VDDE2E_VDD2_GPIO 0
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#define MDDI_RST_N 82
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#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
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#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
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#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
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#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
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#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
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#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
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#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
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#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
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#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
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#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
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#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
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#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
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#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
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#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
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#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
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#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
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#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
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#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
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#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
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#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
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#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
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#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
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#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
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#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
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#define START (LCD_CONTROL_BLOCK_BASE|0x08)
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#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
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#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
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#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
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#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
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#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
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#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
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#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
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#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
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#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
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#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
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#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
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#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
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#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
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#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
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#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
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#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
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#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
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#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
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#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
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#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
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#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
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#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
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#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
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#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
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#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
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#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
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#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
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#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
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#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
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#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
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#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
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#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
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|
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#define SSICTL (SPI_BLOCK_BASE|0x00)
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#define SSITIME (SPI_BLOCK_BASE|0x04)
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#define SSITX (SPI_BLOCK_BASE|0x08)
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#define SSIRX (SPI_BLOCK_BASE|0x0C)
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#define SSIINTC (SPI_BLOCK_BASE|0x10)
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#define SSIINTS (SPI_BLOCK_BASE|0x14)
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#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
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#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
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#define SSIID (SPI_BLOCK_BASE|0x20)
|
||||
|
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#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
|
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#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
|
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#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
|
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#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
|
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#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
|
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|
||||
#define GPIODATA (GPIO_BLOCK_BASE|0x00)
|
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#define GPIODIR (GPIO_BLOCK_BASE|0x04)
|
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#define GPIOIS (GPIO_BLOCK_BASE|0x08)
|
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#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
|
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#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
|
||||
#define GPIOIE (GPIO_BLOCK_BASE|0x14)
|
||||
#define GPIORIS (GPIO_BLOCK_BASE|0x18)
|
||||
#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
|
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#define GPIOIC (GPIO_BLOCK_BASE|0x20)
|
||||
#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
|
||||
#define GPIOPC (GPIO_BLOCK_BASE|0x28)
|
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#define GPIOID (GPIO_BLOCK_BASE|0x30)
|
||||
|
||||
#define SPI_WRITE(reg, val) \
|
||||
{ SSITX, 0x00010000 | (((reg) & 0xff) << 8) | ((val) & 0xff) }, \
|
||||
{ 0, 5 },
|
||||
|
||||
#define SPI_WRITE1(reg) \
|
||||
{ SSITX, (reg) & 0xff }, \
|
||||
{ 0, 5 },
|
||||
|
||||
struct mddi_table {
|
||||
uint32_t reg;
|
||||
uint32_t value;
|
||||
};
|
||||
static struct mddi_table mddi_toshiba_init_table[] = {
|
||||
{ DPSET0, 0x09e90046 },
|
||||
{ DPSET1, 0x00000118 },
|
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{ DPSUS, 0x00000000 },
|
||||
{ DPRUN, 0x00000001 },
|
||||
{ 1, 14 }, /* msleep 14 */
|
||||
{ SYSCKENA, 0x00000001 },
|
||||
{ CLKENB, 0x0000A1EF }, /* # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK) */
|
||||
|
||||
{ GPIODATA, 0x02000200 }, /* # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 */
|
||||
{ GPIODIR, 0x000030D }, /* 24D # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output) */
|
||||
{ GPIOSEL, 0/*0x00000173*/}, /* # SYS.GPIOSEL # GPIO port multiplexing control */
|
||||
{ GPIOPC, 0x03C300C0 }, /* # GPI .GPIOPC # GPIO2,3 PD cut */
|
||||
{ WKREQ, 0x00000000 }, /* # SYS.WKREQ # Wake-up request event is VSYNC alignment */
|
||||
|
||||
{ GPIOIBE, 0x000003FF },
|
||||
{ GPIOIS, 0x00000000 },
|
||||
{ GPIOIC, 0x000003FF },
|
||||
{ GPIOIE, 0x00000000 },
|
||||
|
||||
{ GPIODATA, 0x00040004 }, /* # GPI .GPIODATA # eDRAM VD supply */
|
||||
{ 1, 1 }, /* msleep 1 */
|
||||
{ GPIODATA, 0x02040004 }, /* # GPI .GPIODATA # eDRAM VD supply */
|
||||
{ DRAMPWR, 0x00000001 }, /* eDRAM power */
|
||||
};
|
||||
|
||||
#define GPIOSEL_VWAKEINT (1U << 0)
|
||||
#define INTMASK_VWAKEOUT (1U << 0)
|
||||
|
||||
|
||||
static struct clk *gp_clk;
|
||||
static int trout_new_backlight = 1;
|
||||
static struct vreg *vreg_mddi_1v5;
|
||||
static struct vreg *vreg_lcm_2v85;
|
||||
|
||||
static void trout_process_mddi_table(struct msm_mddi_client_data *client_data,
|
||||
struct mddi_table *table, size_t count)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < count; i++) {
|
||||
uint32_t reg = table[i].reg;
|
||||
uint32_t value = table[i].value;
|
||||
|
||||
if (reg == 0)
|
||||
udelay(value);
|
||||
else if (reg == 1)
|
||||
msleep(value);
|
||||
else
|
||||
client_data->remote_write(client_data, value, reg);
|
||||
}
|
||||
}
|
||||
|
||||
static int trout_mddi_toshiba_client_init(
|
||||
struct msm_mddi_bridge_platform_data *bridge_data,
|
||||
struct msm_mddi_client_data *client_data)
|
||||
{
|
||||
int panel_id;
|
||||
|
||||
client_data->auto_hibernate(client_data, 0);
|
||||
trout_process_mddi_table(client_data, mddi_toshiba_init_table,
|
||||
ARRAY_SIZE(mddi_toshiba_init_table));
|
||||
client_data->auto_hibernate(client_data, 1);
|
||||
panel_id = (client_data->remote_read(client_data, GPIODATA) >> 4) & 3;
|
||||
if (panel_id > 1) {
|
||||
printk(KERN_WARNING "unknown panel id at mddi_enable\n");
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int trout_mddi_toshiba_client_uninit(
|
||||
struct msm_mddi_bridge_platform_data *bridge_data,
|
||||
struct msm_mddi_client_data *client_data)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct resource resources_msm_fb[] = {
|
||||
{
|
||||
.start = MSM_FB_BASE,
|
||||
.end = MSM_FB_BASE + MSM_FB_SIZE,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
struct msm_mddi_bridge_platform_data toshiba_client_data = {
|
||||
.init = trout_mddi_toshiba_client_init,
|
||||
.uninit = trout_mddi_toshiba_client_uninit,
|
||||
.fb_data = {
|
||||
.xres = 320,
|
||||
.yres = 480,
|
||||
.width = 45,
|
||||
.height = 67,
|
||||
.output_format = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_mddi_platform_data mddi_pdata = {
|
||||
.clk_rate = 122880000,
|
||||
.fb_resource = resources_msm_fb,
|
||||
.num_clients = 1,
|
||||
.client_platform_data = {
|
||||
{
|
||||
.product_id = (0xd263 << 16 | 0),
|
||||
.name = "mddi_c_d263_0000",
|
||||
.id = 0,
|
||||
.client_data = &toshiba_client_data,
|
||||
.clk_rate = 0,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
int __init trout_init_panel(void)
|
||||
{
|
||||
int rc;
|
||||
|
||||
if (!machine_is_trout())
|
||||
return 0;
|
||||
vreg_mddi_1v5 = vreg_get(0, "gp2");
|
||||
if (IS_ERR(vreg_mddi_1v5))
|
||||
return PTR_ERR(vreg_mddi_1v5);
|
||||
vreg_lcm_2v85 = vreg_get(0, "gp4");
|
||||
if (IS_ERR(vreg_lcm_2v85))
|
||||
return PTR_ERR(vreg_lcm_2v85);
|
||||
|
||||
trout_new_backlight = system_rev >= 5;
|
||||
if (trout_new_backlight) {
|
||||
uint32_t config = PCOM_GPIO_CFG(27, 0, GPIO_OUTPUT,
|
||||
GPIO_NO_PULL, GPIO_8MA);
|
||||
msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
|
||||
} else {
|
||||
uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT,
|
||||
GPIO_NO_PULL, GPIO_8MA);
|
||||
msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
|
||||
|
||||
gp_clk = clk_get(NULL, "gp_clk");
|
||||
if (IS_ERR(gp_clk)) {
|
||||
printk(KERN_ERR "trout_init_panel: could not get gp"
|
||||
"clock\n");
|
||||
gp_clk = NULL;
|
||||
}
|
||||
rc = clk_set_rate(gp_clk, 19200000);
|
||||
if (rc)
|
||||
printk(KERN_ERR "trout_init_panel: set clock rate "
|
||||
"failed\n");
|
||||
}
|
||||
|
||||
rc = platform_device_register(&msm_device_mdp);
|
||||
if (rc)
|
||||
return rc;
|
||||
msm_device_mddi0.dev.platform_data = &mddi_pdata;
|
||||
return platform_device_register(&msm_device_mddi0);
|
||||
}
|
||||
|
||||
device_initcall(trout_init_panel);
|
|
@ -120,6 +120,21 @@ EXPORT_SYMBOL(clk_get_rate);
|
|||
|
||||
int clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
int ret;
|
||||
if (clk->flags & CLKFLAG_MAX) {
|
||||
ret = clk->ops->set_max_rate(clk->id, rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
if (clk->flags & CLKFLAG_MIN) {
|
||||
ret = clk->ops->set_min_rate(clk->id, rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (clk->flags & CLKFLAG_MAX || clk->flags & CLKFLAG_MIN)
|
||||
return ret;
|
||||
|
||||
return clk->ops->set_rate(clk->id, rate);
|
||||
}
|
||||
EXPORT_SYMBOL(clk_set_rate);
|
||||
|
|
|
@ -347,6 +347,73 @@ int __init msm_add_sdcc(unsigned int controller,
|
|||
return platform_device_register(pdev);
|
||||
}
|
||||
|
||||
static struct resource resources_mddi0[] = {
|
||||
{
|
||||
.start = MSM_PMDH_PHYS,
|
||||
.end = MSM_PMDH_PHYS + MSM_PMDH_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = INT_MDDI_PRI,
|
||||
.end = INT_MDDI_PRI,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource resources_mddi1[] = {
|
||||
{
|
||||
.start = MSM_EMDH_PHYS,
|
||||
.end = MSM_EMDH_PHYS + MSM_EMDH_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = INT_MDDI_EXT,
|
||||
.end = INT_MDDI_EXT,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device msm_device_mddi0 = {
|
||||
.name = "msm_mddi",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(resources_mddi0),
|
||||
.resource = resources_mddi0,
|
||||
.dev = {
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device msm_device_mddi1 = {
|
||||
.name = "msm_mddi",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(resources_mddi1),
|
||||
.resource = resources_mddi1,
|
||||
.dev = {
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource resources_mdp[] = {
|
||||
{
|
||||
.start = MSM_MDP_PHYS,
|
||||
.end = MSM_MDP_PHYS + MSM_MDP_SIZE - 1,
|
||||
.name = "mdp",
|
||||
.flags = IORESOURCE_MEM
|
||||
},
|
||||
{
|
||||
.start = INT_MDP,
|
||||
.end = INT_MDP,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device msm_device_mdp = {
|
||||
.name = "msm_mdp",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(resources_mdp),
|
||||
.resource = resources_mdp,
|
||||
};
|
||||
|
||||
struct clk msm_clocks_7x01a[] = {
|
||||
CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
|
||||
CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0),
|
||||
|
@ -364,7 +431,7 @@ struct clk msm_clocks_7x01a[] = {
|
|||
CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF),
|
||||
CLK_PCOM("pbus_clk", PBUS_CLK, NULL, 0),
|
||||
CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0),
|
||||
CLK_PCOM("pmdh_clk", PMDH_CLK, NULL, OFF ),
|
||||
CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX),
|
||||
CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
|
||||
CLK_PCOM("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF),
|
||||
CLK_PCOM("sdc_pclk", SDC1_P_CLK, &msm_device_sdc1.dev, OFF),
|
||||
|
|
|
@ -56,6 +56,77 @@ struct platform_device msm_device_smd = {
|
|||
.id = -1,
|
||||
};
|
||||
|
||||
static struct resource resources_otg[] = {
|
||||
{
|
||||
.start = MSM_HSUSB_PHYS,
|
||||
.end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = INT_USB_HS,
|
||||
.end = INT_USB_HS,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device msm_device_otg = {
|
||||
.name = "msm_otg",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(resources_otg),
|
||||
.resource = resources_otg,
|
||||
.dev = {
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource resources_hsusb[] = {
|
||||
{
|
||||
.start = MSM_HSUSB_PHYS,
|
||||
.end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = INT_USB_HS,
|
||||
.end = INT_USB_HS,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device msm_device_hsusb = {
|
||||
.name = "msm_hsusb",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(resources_hsusb),
|
||||
.resource = resources_hsusb,
|
||||
.dev = {
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
};
|
||||
|
||||
static u64 dma_mask = 0xffffffffULL;
|
||||
static struct resource resources_hsusb_host[] = {
|
||||
{
|
||||
.start = MSM_HSUSB_PHYS,
|
||||
.end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = INT_USB_HS,
|
||||
.end = INT_USB_HS,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device msm_device_hsusb_host = {
|
||||
.name = "msm_hsusb_host",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(resources_hsusb_host),
|
||||
.resource = resources_hsusb_host,
|
||||
.dev = {
|
||||
.dma_mask = &dma_mask,
|
||||
.coherent_dma_mask = 0xffffffffULL,
|
||||
},
|
||||
};
|
||||
|
||||
struct clk msm_clocks_7x30[] = {
|
||||
CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
|
||||
CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0),
|
||||
|
@ -107,6 +178,7 @@ struct clk msm_clocks_7x30[] = {
|
|||
CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0),
|
||||
CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0),
|
||||
CLK_PCOM("uart_clk", UART2_CLK, &msm_device_uart2.dev, 0),
|
||||
CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0),
|
||||
CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF),
|
||||
CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF),
|
||||
CLK_PCOM("usb_hs_core_clk", USB_HS_CORE_CLK, NULL, OFF),
|
||||
|
|
|
@ -254,60 +254,86 @@ static struct resource msm_iommu_gfx2d0_resources[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct resource msm_iommu_gfx2d1_resources[] = {
|
||||
{
|
||||
.start = MSM_IOMMU_GFX2D1_PHYS,
|
||||
.end = MSM_IOMMU_GFX2D1_PHYS + MSM_IOMMU_GFX2D1_SIZE - 1,
|
||||
.name = "physbase",
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.name = "nonsecure_irq",
|
||||
.start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
|
||||
.end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.name = "secure_irq",
|
||||
.start = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
|
||||
.end = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device msm_root_iommu_dev = {
|
||||
.name = "msm_iommu",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
static struct msm_iommu_dev jpegd_smmu = {
|
||||
static struct msm_iommu_dev jpegd_iommu = {
|
||||
.name = "jpegd",
|
||||
.clk_rate = -1
|
||||
};
|
||||
|
||||
static struct msm_iommu_dev vpe_smmu = {
|
||||
static struct msm_iommu_dev vpe_iommu = {
|
||||
.name = "vpe"
|
||||
};
|
||||
|
||||
static struct msm_iommu_dev mdp0_smmu = {
|
||||
static struct msm_iommu_dev mdp0_iommu = {
|
||||
.name = "mdp0"
|
||||
};
|
||||
|
||||
static struct msm_iommu_dev mdp1_smmu = {
|
||||
static struct msm_iommu_dev mdp1_iommu = {
|
||||
.name = "mdp1"
|
||||
};
|
||||
|
||||
static struct msm_iommu_dev rot_smmu = {
|
||||
static struct msm_iommu_dev rot_iommu = {
|
||||
.name = "rot"
|
||||
};
|
||||
|
||||
static struct msm_iommu_dev ijpeg_smmu = {
|
||||
static struct msm_iommu_dev ijpeg_iommu = {
|
||||
.name = "ijpeg"
|
||||
};
|
||||
|
||||
static struct msm_iommu_dev vfe_smmu = {
|
||||
static struct msm_iommu_dev vfe_iommu = {
|
||||
.name = "vfe",
|
||||
.clk_rate = -1
|
||||
};
|
||||
|
||||
static struct msm_iommu_dev vcodec_a_smmu = {
|
||||
static struct msm_iommu_dev vcodec_a_iommu = {
|
||||
.name = "vcodec_a"
|
||||
};
|
||||
|
||||
static struct msm_iommu_dev vcodec_b_smmu = {
|
||||
static struct msm_iommu_dev vcodec_b_iommu = {
|
||||
.name = "vcodec_b"
|
||||
};
|
||||
|
||||
static struct msm_iommu_dev gfx3d_smmu = {
|
||||
static struct msm_iommu_dev gfx3d_iommu = {
|
||||
.name = "gfx3d",
|
||||
.clk_rate = 27000000
|
||||
};
|
||||
|
||||
static struct msm_iommu_dev gfx2d0_smmu = {
|
||||
static struct msm_iommu_dev gfx2d0_iommu = {
|
||||
.name = "gfx2d0",
|
||||
.clk_rate = 27000000
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_smmu_jpegd = {
|
||||
static struct msm_iommu_dev gfx2d1_iommu = {
|
||||
.name = "gfx2d1",
|
||||
.clk_rate = 27000000
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_iommu_jpegd = {
|
||||
.name = "msm_iommu",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
|
@ -317,7 +343,7 @@ static struct platform_device msm_device_smmu_jpegd = {
|
|||
.resource = msm_iommu_jpegd_resources,
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_smmu_vpe = {
|
||||
static struct platform_device msm_device_iommu_vpe = {
|
||||
.name = "msm_iommu",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
|
@ -327,7 +353,7 @@ static struct platform_device msm_device_smmu_vpe = {
|
|||
.resource = msm_iommu_vpe_resources,
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_smmu_mdp0 = {
|
||||
static struct platform_device msm_device_iommu_mdp0 = {
|
||||
.name = "msm_iommu",
|
||||
.id = 2,
|
||||
.dev = {
|
||||
|
@ -337,7 +363,7 @@ static struct platform_device msm_device_smmu_mdp0 = {
|
|||
.resource = msm_iommu_mdp0_resources,
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_smmu_mdp1 = {
|
||||
static struct platform_device msm_device_iommu_mdp1 = {
|
||||
.name = "msm_iommu",
|
||||
.id = 3,
|
||||
.dev = {
|
||||
|
@ -347,7 +373,7 @@ static struct platform_device msm_device_smmu_mdp1 = {
|
|||
.resource = msm_iommu_mdp1_resources,
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_smmu_rot = {
|
||||
static struct platform_device msm_device_iommu_rot = {
|
||||
.name = "msm_iommu",
|
||||
.id = 4,
|
||||
.dev = {
|
||||
|
@ -357,7 +383,7 @@ static struct platform_device msm_device_smmu_rot = {
|
|||
.resource = msm_iommu_rot_resources,
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_smmu_ijpeg = {
|
||||
static struct platform_device msm_device_iommu_ijpeg = {
|
||||
.name = "msm_iommu",
|
||||
.id = 5,
|
||||
.dev = {
|
||||
|
@ -367,7 +393,7 @@ static struct platform_device msm_device_smmu_ijpeg = {
|
|||
.resource = msm_iommu_ijpeg_resources,
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_smmu_vfe = {
|
||||
static struct platform_device msm_device_iommu_vfe = {
|
||||
.name = "msm_iommu",
|
||||
.id = 6,
|
||||
.dev = {
|
||||
|
@ -377,7 +403,7 @@ static struct platform_device msm_device_smmu_vfe = {
|
|||
.resource = msm_iommu_vfe_resources,
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_smmu_vcodec_a = {
|
||||
static struct platform_device msm_device_iommu_vcodec_a = {
|
||||
.name = "msm_iommu",
|
||||
.id = 7,
|
||||
.dev = {
|
||||
|
@ -387,7 +413,7 @@ static struct platform_device msm_device_smmu_vcodec_a = {
|
|||
.resource = msm_iommu_vcodec_a_resources,
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_smmu_vcodec_b = {
|
||||
static struct platform_device msm_device_iommu_vcodec_b = {
|
||||
.name = "msm_iommu",
|
||||
.id = 8,
|
||||
.dev = {
|
||||
|
@ -397,7 +423,7 @@ static struct platform_device msm_device_smmu_vcodec_b = {
|
|||
.resource = msm_iommu_vcodec_b_resources,
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_smmu_gfx3d = {
|
||||
static struct platform_device msm_device_iommu_gfx3d = {
|
||||
.name = "msm_iommu",
|
||||
.id = 9,
|
||||
.dev = {
|
||||
|
@ -407,7 +433,7 @@ static struct platform_device msm_device_smmu_gfx3d = {
|
|||
.resource = msm_iommu_gfx3d_resources,
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_smmu_gfx2d0 = {
|
||||
static struct platform_device msm_device_iommu_gfx2d0 = {
|
||||
.name = "msm_iommu",
|
||||
.id = 10,
|
||||
.dev = {
|
||||
|
@ -417,6 +443,16 @@ static struct platform_device msm_device_smmu_gfx2d0 = {
|
|||
.resource = msm_iommu_gfx2d0_resources,
|
||||
};
|
||||
|
||||
struct platform_device msm_device_iommu_gfx2d1 = {
|
||||
.name = "msm_iommu",
|
||||
.id = 11,
|
||||
.dev = {
|
||||
.parent = &msm_root_iommu_dev.dev,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources),
|
||||
.resource = msm_iommu_gfx2d1_resources,
|
||||
};
|
||||
|
||||
static struct msm_iommu_ctx_dev jpegd_src_ctx = {
|
||||
.name = "jpegd_src",
|
||||
.num = 0,
|
||||
|
@ -519,41 +555,36 @@ static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = {
|
|||
.mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
|
||||
};
|
||||
|
||||
static struct msm_iommu_ctx_dev gfx3d_rbpa_ctx = {
|
||||
.name = "gfx3d_rbpa",
|
||||
static struct msm_iommu_ctx_dev gfx3d_user_ctx = {
|
||||
.name = "gfx3d_user",
|
||||
.num = 0,
|
||||
.mids = {-1}
|
||||
.mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
|
||||
};
|
||||
|
||||
static struct msm_iommu_ctx_dev gfx3d_cpvgttc_ctx = {
|
||||
.name = "gfx3d_cpvgttc",
|
||||
static struct msm_iommu_ctx_dev gfx3d_priv_ctx = {
|
||||
.name = "gfx3d_priv",
|
||||
.num = 1,
|
||||
.mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
|
||||
31, -1}
|
||||
};
|
||||
|
||||
static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = {
|
||||
.name = "gfx2d0_2d0",
|
||||
.num = 0,
|
||||
.mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
|
||||
};
|
||||
|
||||
static struct msm_iommu_ctx_dev gfx3d_smmu_ctx = {
|
||||
.name = "gfx3d_smmu",
|
||||
.num = 2,
|
||||
.mids = {8, 9, 10, 11, 12, -1}
|
||||
};
|
||||
|
||||
static struct msm_iommu_ctx_dev gfx2d0_pixv1_ctx = {
|
||||
.name = "gfx2d0_pixv1_smmu",
|
||||
static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = {
|
||||
.name = "gfx2d1_2d1",
|
||||
.num = 0,
|
||||
.mids = {0, 3, 4, -1}
|
||||
};
|
||||
|
||||
static struct msm_iommu_ctx_dev gfx2d0_texv3_ctx = {
|
||||
.name = "gfx2d0_texv3_smmu",
|
||||
.num = 1,
|
||||
.mids = {1, 6, 7, -1}
|
||||
.mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_jpegd_src_ctx = {
|
||||
.name = "msm_iommu_ctx",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_jpegd.dev,
|
||||
.parent = &msm_device_iommu_jpegd.dev,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -561,7 +592,7 @@ static struct platform_device msm_device_jpegd_dst_ctx = {
|
|||
.name = "msm_iommu_ctx",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_jpegd.dev,
|
||||
.parent = &msm_device_iommu_jpegd.dev,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -569,7 +600,7 @@ static struct platform_device msm_device_vpe_src_ctx = {
|
|||
.name = "msm_iommu_ctx",
|
||||
.id = 2,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_vpe.dev,
|
||||
.parent = &msm_device_iommu_vpe.dev,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -577,7 +608,7 @@ static struct platform_device msm_device_vpe_dst_ctx = {
|
|||
.name = "msm_iommu_ctx",
|
||||
.id = 3,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_vpe.dev,
|
||||
.parent = &msm_device_iommu_vpe.dev,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -585,7 +616,7 @@ static struct platform_device msm_device_mdp_vg1_ctx = {
|
|||
.name = "msm_iommu_ctx",
|
||||
.id = 4,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_mdp0.dev,
|
||||
.parent = &msm_device_iommu_mdp0.dev,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -593,7 +624,7 @@ static struct platform_device msm_device_mdp_rgb1_ctx = {
|
|||
.name = "msm_iommu_ctx",
|
||||
.id = 5,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_mdp0.dev,
|
||||
.parent = &msm_device_iommu_mdp0.dev,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -601,7 +632,7 @@ static struct platform_device msm_device_mdp_vg2_ctx = {
|
|||
.name = "msm_iommu_ctx",
|
||||
.id = 6,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_mdp1.dev,
|
||||
.parent = &msm_device_iommu_mdp1.dev,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -609,7 +640,7 @@ static struct platform_device msm_device_mdp_rgb2_ctx = {
|
|||
.name = "msm_iommu_ctx",
|
||||
.id = 7,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_mdp1.dev,
|
||||
.parent = &msm_device_iommu_mdp1.dev,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -617,7 +648,7 @@ static struct platform_device msm_device_rot_src_ctx = {
|
|||
.name = "msm_iommu_ctx",
|
||||
.id = 8,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_rot.dev,
|
||||
.parent = &msm_device_iommu_rot.dev,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -625,7 +656,7 @@ static struct platform_device msm_device_rot_dst_ctx = {
|
|||
.name = "msm_iommu_ctx",
|
||||
.id = 9,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_rot.dev,
|
||||
.parent = &msm_device_iommu_rot.dev,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -633,7 +664,7 @@ static struct platform_device msm_device_ijpeg_src_ctx = {
|
|||
.name = "msm_iommu_ctx",
|
||||
.id = 10,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_ijpeg.dev,
|
||||
.parent = &msm_device_iommu_ijpeg.dev,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -641,7 +672,7 @@ static struct platform_device msm_device_ijpeg_dst_ctx = {
|
|||
.name = "msm_iommu_ctx",
|
||||
.id = 11,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_ijpeg.dev,
|
||||
.parent = &msm_device_iommu_ijpeg.dev,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -649,7 +680,7 @@ static struct platform_device msm_device_vfe_imgwr_ctx = {
|
|||
.name = "msm_iommu_ctx",
|
||||
.id = 12,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_vfe.dev,
|
||||
.parent = &msm_device_iommu_vfe.dev,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -657,7 +688,7 @@ static struct platform_device msm_device_vfe_misc_ctx = {
|
|||
.name = "msm_iommu_ctx",
|
||||
.id = 13,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_vfe.dev,
|
||||
.parent = &msm_device_iommu_vfe.dev,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -665,7 +696,7 @@ static struct platform_device msm_device_vcodec_a_stream_ctx = {
|
|||
.name = "msm_iommu_ctx",
|
||||
.id = 14,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_vcodec_a.dev,
|
||||
.parent = &msm_device_iommu_vcodec_a.dev,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -673,7 +704,7 @@ static struct platform_device msm_device_vcodec_a_mm1_ctx = {
|
|||
.name = "msm_iommu_ctx",
|
||||
.id = 15,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_vcodec_a.dev,
|
||||
.parent = &msm_device_iommu_vcodec_a.dev,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -681,76 +712,70 @@ static struct platform_device msm_device_vcodec_b_mm2_ctx = {
|
|||
.name = "msm_iommu_ctx",
|
||||
.id = 16,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_vcodec_b.dev,
|
||||
.parent = &msm_device_iommu_vcodec_b.dev,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_gfx3d_rbpa_ctx = {
|
||||
static struct platform_device msm_device_gfx3d_user_ctx = {
|
||||
.name = "msm_iommu_ctx",
|
||||
.id = 17,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_gfx3d.dev,
|
||||
.parent = &msm_device_iommu_gfx3d.dev,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_gfx3d_cpvgttc_ctx = {
|
||||
static struct platform_device msm_device_gfx3d_priv_ctx = {
|
||||
.name = "msm_iommu_ctx",
|
||||
.id = 18,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_gfx3d.dev,
|
||||
.parent = &msm_device_iommu_gfx3d.dev,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_gfx3d_smmu_ctx = {
|
||||
static struct platform_device msm_device_gfx2d0_2d0_ctx = {
|
||||
.name = "msm_iommu_ctx",
|
||||
.id = 19,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_gfx3d.dev,
|
||||
.parent = &msm_device_iommu_gfx2d0.dev,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_gfx2d0_pixv1_ctx = {
|
||||
static struct platform_device msm_device_gfx2d1_2d1_ctx = {
|
||||
.name = "msm_iommu_ctx",
|
||||
.id = 20,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_gfx2d0.dev,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_gfx2d0_texv3_ctx = {
|
||||
.name = "msm_iommu_ctx",
|
||||
.id = 21,
|
||||
.dev = {
|
||||
.parent = &msm_device_smmu_gfx2d0.dev,
|
||||
.parent = &msm_device_iommu_gfx2d1.dev,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *msm_iommu_devs[] = {
|
||||
&msm_device_smmu_jpegd,
|
||||
&msm_device_smmu_vpe,
|
||||
&msm_device_smmu_mdp0,
|
||||
&msm_device_smmu_mdp1,
|
||||
&msm_device_smmu_rot,
|
||||
&msm_device_smmu_ijpeg,
|
||||
&msm_device_smmu_vfe,
|
||||
&msm_device_smmu_vcodec_a,
|
||||
&msm_device_smmu_vcodec_b,
|
||||
&msm_device_smmu_gfx3d,
|
||||
&msm_device_smmu_gfx2d0,
|
||||
&msm_device_iommu_jpegd,
|
||||
&msm_device_iommu_vpe,
|
||||
&msm_device_iommu_mdp0,
|
||||
&msm_device_iommu_mdp1,
|
||||
&msm_device_iommu_rot,
|
||||
&msm_device_iommu_ijpeg,
|
||||
&msm_device_iommu_vfe,
|
||||
&msm_device_iommu_vcodec_a,
|
||||
&msm_device_iommu_vcodec_b,
|
||||
&msm_device_iommu_gfx3d,
|
||||
&msm_device_iommu_gfx2d0,
|
||||
&msm_device_iommu_gfx2d1,
|
||||
};
|
||||
|
||||
static struct msm_iommu_dev *msm_iommu_data[] = {
|
||||
&jpegd_smmu,
|
||||
&vpe_smmu,
|
||||
&mdp0_smmu,
|
||||
&mdp1_smmu,
|
||||
&rot_smmu,
|
||||
&ijpeg_smmu,
|
||||
&vfe_smmu,
|
||||
&vcodec_a_smmu,
|
||||
&vcodec_b_smmu,
|
||||
&gfx3d_smmu,
|
||||
&gfx2d0_smmu,
|
||||
&jpegd_iommu,
|
||||
&vpe_iommu,
|
||||
&mdp0_iommu,
|
||||
&mdp1_iommu,
|
||||
&rot_iommu,
|
||||
&ijpeg_iommu,
|
||||
&vfe_iommu,
|
||||
&vcodec_a_iommu,
|
||||
&vcodec_b_iommu,
|
||||
&gfx3d_iommu,
|
||||
&gfx2d0_iommu,
|
||||
&gfx2d1_iommu,
|
||||
};
|
||||
|
||||
static struct platform_device *msm_iommu_ctx_devs[] = {
|
||||
|
@ -771,11 +796,10 @@ static struct platform_device *msm_iommu_ctx_devs[] = {
|
|||
&msm_device_vcodec_a_stream_ctx,
|
||||
&msm_device_vcodec_a_mm1_ctx,
|
||||
&msm_device_vcodec_b_mm2_ctx,
|
||||
&msm_device_gfx3d_rbpa_ctx,
|
||||
&msm_device_gfx3d_cpvgttc_ctx,
|
||||
&msm_device_gfx3d_smmu_ctx,
|
||||
&msm_device_gfx2d0_pixv1_ctx,
|
||||
&msm_device_gfx2d0_texv3_ctx,
|
||||
&msm_device_gfx3d_user_ctx,
|
||||
&msm_device_gfx3d_priv_ctx,
|
||||
&msm_device_gfx2d0_2d0_ctx,
|
||||
&msm_device_gfx2d1_2d1_ctx,
|
||||
};
|
||||
|
||||
static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
|
||||
|
@ -796,14 +820,13 @@ static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
|
|||
&vcodec_a_stream_ctx,
|
||||
&vcodec_a_mm1_ctx,
|
||||
&vcodec_b_mm2_ctx,
|
||||
&gfx3d_rbpa_ctx,
|
||||
&gfx3d_cpvgttc_ctx,
|
||||
&gfx3d_smmu_ctx,
|
||||
&gfx2d0_pixv1_ctx,
|
||||
&gfx2d0_texv3_ctx,
|
||||
&gfx3d_user_ctx,
|
||||
&gfx3d_priv_ctx,
|
||||
&gfx2d0_2d0_ctx,
|
||||
&gfx2d1_2d1_ctx,
|
||||
};
|
||||
|
||||
static int msm8x60_iommu_init(void)
|
||||
static int __init msm8x60_iommu_init(void)
|
||||
{
|
||||
int ret, i;
|
||||
|
||||
|
@ -826,7 +849,7 @@ static int msm8x60_iommu_init(void)
|
|||
ret = platform_device_register(msm_iommu_devs[i]);
|
||||
|
||||
if (ret != 0) {
|
||||
pr_err("platform_device_register smmu failed, "
|
||||
pr_err("platform_device_register iommu failed, "
|
||||
"i = %d\n", i);
|
||||
goto failure_unwind;
|
||||
}
|
||||
|
@ -837,7 +860,7 @@ static int msm8x60_iommu_init(void)
|
|||
msm_iommu_ctx_data[i],
|
||||
sizeof(*msm_iommu_ctx_devs[i]));
|
||||
if (ret != 0) {
|
||||
pr_err("platform_device_add_data smmu failed, "
|
||||
pr_err("platform_device_add_data iommu failed, "
|
||||
"i = %d\n", i);
|
||||
goto failure_unwind2;
|
||||
}
|
||||
|
@ -863,7 +886,7 @@ failure:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void msm8x60_iommu_exit(void)
|
||||
static void __exit msm8x60_iommu_exit(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
|
@ -53,6 +53,77 @@ struct platform_device msm_device_smd = {
|
|||
.id = -1,
|
||||
};
|
||||
|
||||
static struct resource resources_otg[] = {
|
||||
{
|
||||
.start = MSM_HSUSB_PHYS,
|
||||
.end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = INT_USB_HS,
|
||||
.end = INT_USB_HS,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device msm_device_otg = {
|
||||
.name = "msm_otg",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(resources_otg),
|
||||
.resource = resources_otg,
|
||||
.dev = {
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource resources_hsusb[] = {
|
||||
{
|
||||
.start = MSM_HSUSB_PHYS,
|
||||
.end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = INT_USB_HS,
|
||||
.end = INT_USB_HS,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device msm_device_hsusb = {
|
||||
.name = "msm_hsusb",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(resources_hsusb),
|
||||
.resource = resources_hsusb,
|
||||
.dev = {
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
};
|
||||
|
||||
static u64 dma_mask = 0xffffffffULL;
|
||||
static struct resource resources_hsusb_host[] = {
|
||||
{
|
||||
.start = MSM_HSUSB_PHYS,
|
||||
.end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = INT_USB_HS,
|
||||
.end = INT_USB_HS,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device msm_device_hsusb_host = {
|
||||
.name = "msm_hsusb_host",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(resources_hsusb_host),
|
||||
.resource = resources_hsusb_host,
|
||||
.dev = {
|
||||
.dma_mask = &dma_mask,
|
||||
.coherent_dma_mask = 0xffffffffULL,
|
||||
},
|
||||
};
|
||||
|
||||
struct clk msm_clocks_8x50[] = {
|
||||
CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
|
||||
CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN),
|
||||
|
|
|
@ -28,6 +28,8 @@ extern struct platform_device msm_device_sdc3;
|
|||
extern struct platform_device msm_device_sdc4;
|
||||
|
||||
extern struct platform_device msm_device_hsusb;
|
||||
extern struct platform_device msm_device_otg;
|
||||
extern struct platform_device msm_device_hsusb_host;
|
||||
|
||||
extern struct platform_device msm_device_i2c;
|
||||
|
||||
|
@ -35,6 +37,10 @@ extern struct platform_device msm_device_smd;
|
|||
|
||||
extern struct platform_device msm_device_nand;
|
||||
|
||||
extern struct platform_device msm_device_mddi0;
|
||||
extern struct platform_device msm_device_mddi1;
|
||||
extern struct platform_device msm_device_mdp;
|
||||
|
||||
extern struct clk msm_clocks_7x01a[];
|
||||
extern unsigned msm_num_clocks_7x01a;
|
||||
|
||||
|
|
|
@ -0,0 +1,426 @@
|
|||
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
* 02110-1301, USA.
|
||||
*
|
||||
*/
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
#include <linux/bitmap.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <mach/msm_iomap.h>
|
||||
#include "gpiomux.h"
|
||||
|
||||
/* Bits of interest in the GPIO_IN_OUT register.
|
||||
*/
|
||||
enum {
|
||||
GPIO_IN = 0,
|
||||
GPIO_OUT = 1
|
||||
};
|
||||
|
||||
/* Bits of interest in the GPIO_INTR_STATUS register.
|
||||
*/
|
||||
enum {
|
||||
INTR_STATUS = 0,
|
||||
};
|
||||
|
||||
/* Bits of interest in the GPIO_CFG register.
|
||||
*/
|
||||
enum {
|
||||
GPIO_OE = 9,
|
||||
};
|
||||
|
||||
/* Bits of interest in the GPIO_INTR_CFG register.
|
||||
* When a GPIO triggers, two separate decisions are made, controlled
|
||||
* by two separate flags.
|
||||
*
|
||||
* - First, INTR_RAW_STATUS_EN controls whether or not the GPIO_INTR_STATUS
|
||||
* register for that GPIO will be updated to reflect the triggering of that
|
||||
* gpio. If this bit is 0, this register will not be updated.
|
||||
* - Second, INTR_ENABLE controls whether an interrupt is triggered.
|
||||
*
|
||||
* If INTR_ENABLE is set and INTR_RAW_STATUS_EN is NOT set, an interrupt
|
||||
* can be triggered but the status register will not reflect it.
|
||||
*/
|
||||
enum {
|
||||
INTR_ENABLE = 0,
|
||||
INTR_POL_CTL = 1,
|
||||
INTR_DECT_CTL = 2,
|
||||
INTR_RAW_STATUS_EN = 3,
|
||||
};
|
||||
|
||||
/* Codes of interest in GPIO_INTR_CFG_SU.
|
||||
*/
|
||||
enum {
|
||||
TARGET_PROC_SCORPION = 4,
|
||||
TARGET_PROC_NONE = 7,
|
||||
};
|
||||
|
||||
|
||||
#define GPIO_INTR_CFG_SU(gpio) (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio)))
|
||||
#define GPIO_CONFIG(gpio) (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio)))
|
||||
#define GPIO_IN_OUT(gpio) (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio)))
|
||||
#define GPIO_INTR_CFG(gpio) (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio)))
|
||||
#define GPIO_INTR_STATUS(gpio) (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio)))
|
||||
|
||||
/**
|
||||
* struct msm_gpio_dev: the MSM8660 SoC GPIO device structure
|
||||
*
|
||||
* @enabled_irqs: a bitmap used to optimize the summary-irq handler. By
|
||||
* keeping track of which gpios are unmasked as irq sources, we avoid
|
||||
* having to do readl calls on hundreds of iomapped registers each time
|
||||
* the summary interrupt fires in order to locate the active interrupts.
|
||||
*
|
||||
* @wake_irqs: a bitmap for tracking which interrupt lines are enabled
|
||||
* as wakeup sources. When the device is suspended, interrupts which are
|
||||
* not wakeup sources are disabled.
|
||||
*
|
||||
* @dual_edge_irqs: a bitmap used to track which irqs are configured
|
||||
* as dual-edge, as this is not supported by the hardware and requires
|
||||
* some special handling in the driver.
|
||||
*/
|
||||
struct msm_gpio_dev {
|
||||
struct gpio_chip gpio_chip;
|
||||
DECLARE_BITMAP(enabled_irqs, NR_GPIO_IRQS);
|
||||
DECLARE_BITMAP(wake_irqs, NR_GPIO_IRQS);
|
||||
DECLARE_BITMAP(dual_edge_irqs, NR_GPIO_IRQS);
|
||||
};
|
||||
|
||||
static DEFINE_SPINLOCK(tlmm_lock);
|
||||
|
||||
static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip)
|
||||
{
|
||||
return container_of(chip, struct msm_gpio_dev, gpio_chip);
|
||||
}
|
||||
|
||||
static inline void set_gpio_bits(unsigned n, void __iomem *reg)
|
||||
{
|
||||
writel(readl(reg) | n, reg);
|
||||
}
|
||||
|
||||
static inline void clear_gpio_bits(unsigned n, void __iomem *reg)
|
||||
{
|
||||
writel(readl(reg) & ~n, reg);
|
||||
}
|
||||
|
||||
static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN);
|
||||
}
|
||||
|
||||
static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
|
||||
{
|
||||
writel(val ? BIT(GPIO_OUT) : 0, GPIO_IN_OUT(offset));
|
||||
}
|
||||
|
||||
static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
unsigned long irq_flags;
|
||||
|
||||
spin_lock_irqsave(&tlmm_lock, irq_flags);
|
||||
clear_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
|
||||
spin_unlock_irqrestore(&tlmm_lock, irq_flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int msm_gpio_direction_output(struct gpio_chip *chip,
|
||||
unsigned offset,
|
||||
int val)
|
||||
{
|
||||
unsigned long irq_flags;
|
||||
|
||||
spin_lock_irqsave(&tlmm_lock, irq_flags);
|
||||
msm_gpio_set(chip, offset, val);
|
||||
set_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
|
||||
spin_unlock_irqrestore(&tlmm_lock, irq_flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
return msm_gpiomux_get(chip->base + offset);
|
||||
}
|
||||
|
||||
static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
msm_gpiomux_put(chip->base + offset);
|
||||
}
|
||||
|
||||
static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
return MSM_GPIO_TO_INT(chip->base + offset);
|
||||
}
|
||||
|
||||
static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq)
|
||||
{
|
||||
return irq - MSM_GPIO_TO_INT(chip->base);
|
||||
}
|
||||
|
||||
static struct msm_gpio_dev msm_gpio = {
|
||||
.gpio_chip = {
|
||||
.base = 0,
|
||||
.ngpio = NR_GPIO_IRQS,
|
||||
.direction_input = msm_gpio_direction_input,
|
||||
.direction_output = msm_gpio_direction_output,
|
||||
.get = msm_gpio_get,
|
||||
.set = msm_gpio_set,
|
||||
.to_irq = msm_gpio_to_irq,
|
||||
.request = msm_gpio_request,
|
||||
.free = msm_gpio_free,
|
||||
},
|
||||
};
|
||||
|
||||
/* For dual-edge interrupts in software, since the hardware has no
|
||||
* such support:
|
||||
*
|
||||
* At appropriate moments, this function may be called to flip the polarity
|
||||
* settings of both-edge irq lines to try and catch the next edge.
|
||||
*
|
||||
* The attempt is considered successful if:
|
||||
* - the status bit goes high, indicating that an edge was caught, or
|
||||
* - the input value of the gpio doesn't change during the attempt.
|
||||
* If the value changes twice during the process, that would cause the first
|
||||
* test to fail but would force the second, as two opposite
|
||||
* transitions would cause a detection no matter the polarity setting.
|
||||
*
|
||||
* The do-loop tries to sledge-hammer closed the timing hole between
|
||||
* the initial value-read and the polarity-write - if the line value changes
|
||||
* during that window, an interrupt is lost, the new polarity setting is
|
||||
* incorrect, and the first success test will fail, causing a retry.
|
||||
*
|
||||
* Algorithm comes from Google's msmgpio driver, see mach-msm/gpio.c.
|
||||
*/
|
||||
static void msm_gpio_update_dual_edge_pos(unsigned gpio)
|
||||
{
|
||||
int loop_limit = 100;
|
||||
unsigned val, val2, intstat;
|
||||
|
||||
do {
|
||||
val = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
|
||||
if (val)
|
||||
clear_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
|
||||
else
|
||||
set_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
|
||||
val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
|
||||
intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS);
|
||||
if (intstat || val == val2)
|
||||
return;
|
||||
} while (loop_limit-- > 0);
|
||||
pr_err("dual-edge irq failed to stabilize, "
|
||||
"interrupts dropped. %#08x != %#08x\n",
|
||||
val, val2);
|
||||
}
|
||||
|
||||
static void msm_gpio_irq_ack(unsigned int irq)
|
||||
{
|
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
|
||||
|
||||
writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio));
|
||||
if (test_bit(gpio, msm_gpio.dual_edge_irqs))
|
||||
msm_gpio_update_dual_edge_pos(gpio);
|
||||
}
|
||||
|
||||
static void msm_gpio_irq_mask(unsigned int irq)
|
||||
{
|
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
|
||||
unsigned long irq_flags;
|
||||
|
||||
spin_lock_irqsave(&tlmm_lock, irq_flags);
|
||||
writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio));
|
||||
clear_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio));
|
||||
__clear_bit(gpio, msm_gpio.enabled_irqs);
|
||||
spin_unlock_irqrestore(&tlmm_lock, irq_flags);
|
||||
}
|
||||
|
||||
static void msm_gpio_irq_unmask(unsigned int irq)
|
||||
{
|
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
|
||||
unsigned long irq_flags;
|
||||
|
||||
spin_lock_irqsave(&tlmm_lock, irq_flags);
|
||||
__set_bit(gpio, msm_gpio.enabled_irqs);
|
||||
set_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio));
|
||||
writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio));
|
||||
spin_unlock_irqrestore(&tlmm_lock, irq_flags);
|
||||
}
|
||||
|
||||
static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
|
||||
{
|
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
|
||||
unsigned long irq_flags;
|
||||
uint32_t bits;
|
||||
|
||||
spin_lock_irqsave(&tlmm_lock, irq_flags);
|
||||
|
||||
bits = readl(GPIO_INTR_CFG(gpio));
|
||||
|
||||
if (flow_type & IRQ_TYPE_EDGE_BOTH) {
|
||||
bits |= BIT(INTR_DECT_CTL);
|
||||
irq_desc[irq].handle_irq = handle_edge_irq;
|
||||
if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
|
||||
__set_bit(gpio, msm_gpio.dual_edge_irqs);
|
||||
else
|
||||
__clear_bit(gpio, msm_gpio.dual_edge_irqs);
|
||||
} else {
|
||||
bits &= ~BIT(INTR_DECT_CTL);
|
||||
irq_desc[irq].handle_irq = handle_level_irq;
|
||||
__clear_bit(gpio, msm_gpio.dual_edge_irqs);
|
||||
}
|
||||
|
||||
if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
|
||||
bits |= BIT(INTR_POL_CTL);
|
||||
else
|
||||
bits &= ~BIT(INTR_POL_CTL);
|
||||
|
||||
writel(bits, GPIO_INTR_CFG(gpio));
|
||||
|
||||
if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
|
||||
msm_gpio_update_dual_edge_pos(gpio);
|
||||
|
||||
spin_unlock_irqrestore(&tlmm_lock, irq_flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* When the summary IRQ is raised, any number of GPIO lines may be high.
|
||||
* It is the job of the summary handler to find all those GPIO lines
|
||||
* which have been set as summary IRQ lines and which are triggered,
|
||||
* and to call their interrupt handlers.
|
||||
*/
|
||||
static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
unsigned long i;
|
||||
|
||||
for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
|
||||
i < NR_GPIO_IRQS;
|
||||
i = find_next_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS, i + 1)) {
|
||||
if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS))
|
||||
generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
|
||||
i));
|
||||
}
|
||||
desc->chip->ack(irq);
|
||||
}
|
||||
|
||||
static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
|
||||
{
|
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
|
||||
|
||||
if (on) {
|
||||
if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
|
||||
set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
|
||||
set_bit(gpio, msm_gpio.wake_irqs);
|
||||
} else {
|
||||
clear_bit(gpio, msm_gpio.wake_irqs);
|
||||
if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
|
||||
set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_chip msm_gpio_irq_chip = {
|
||||
.name = "msmgpio",
|
||||
.mask = msm_gpio_irq_mask,
|
||||
.unmask = msm_gpio_irq_unmask,
|
||||
.ack = msm_gpio_irq_ack,
|
||||
.set_type = msm_gpio_irq_set_type,
|
||||
.set_wake = msm_gpio_irq_set_wake,
|
||||
};
|
||||
|
||||
static int __devinit msm_gpio_probe(struct platform_device *dev)
|
||||
{
|
||||
int i, irq, ret;
|
||||
|
||||
bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
|
||||
bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS);
|
||||
bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS);
|
||||
msm_gpio.gpio_chip.label = dev->name;
|
||||
ret = gpiochip_add(&msm_gpio.gpio_chip);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
|
||||
irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
|
||||
set_irq_chip(irq, &msm_gpio_irq_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
|
||||
set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
|
||||
msm_summary_irq_handler);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __devexit msm_gpio_remove(struct platform_device *dev)
|
||||
{
|
||||
int ret = gpiochip_remove(&msm_gpio.gpio_chip);
|
||||
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver msm_gpio_driver = {
|
||||
.probe = msm_gpio_probe,
|
||||
.remove = __devexit_p(msm_gpio_remove),
|
||||
.driver = {
|
||||
.name = "msmgpio",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device msm_device_gpio = {
|
||||
.name = "msmgpio",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
static int __init msm_gpio_init(void)
|
||||
{
|
||||
int rc;
|
||||
|
||||
rc = platform_driver_register(&msm_gpio_driver);
|
||||
if (!rc) {
|
||||
rc = platform_device_register(&msm_device_gpio);
|
||||
if (rc)
|
||||
platform_driver_unregister(&msm_gpio_driver);
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void __exit msm_gpio_exit(void)
|
||||
{
|
||||
platform_device_unregister(&msm_device_gpio);
|
||||
platform_driver_unregister(&msm_gpio_driver);
|
||||
}
|
||||
|
||||
postcore_initcall(msm_gpio_init);
|
||||
module_exit(msm_gpio_exit);
|
||||
|
||||
MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
|
||||
MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:msmgpio");
|
|
@ -20,13 +20,26 @@
|
|||
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
/* Sharability attributes of MSM IOMMU mappings */
|
||||
#define MSM_IOMMU_ATTR_NON_SH 0x0
|
||||
#define MSM_IOMMU_ATTR_SH 0x4
|
||||
|
||||
/* Cacheability attributes of MSM IOMMU mappings */
|
||||
#define MSM_IOMMU_ATTR_NONCACHED 0x0
|
||||
#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1
|
||||
#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2
|
||||
#define MSM_IOMMU_ATTR_CACHED_WT 0x3
|
||||
|
||||
/* Mask for the cache policy attribute */
|
||||
#define MSM_IOMMU_CP_MASK 0x03
|
||||
|
||||
/* Maximum number of Machine IDs that we are allowing to be mapped to the same
|
||||
* context bank. The number of MIDs mapped to the same CB does not affect
|
||||
* performance, but there is a practical limit on how many distinct MIDs may
|
||||
* be present. These mappings are typically determined at design time and are
|
||||
* not expected to change at run time.
|
||||
*/
|
||||
#define MAX_NUM_MIDS 16
|
||||
#define MAX_NUM_MIDS 32
|
||||
|
||||
/**
|
||||
* struct msm_iommu_dev - a single IOMMU hardware instance
|
||||
|
|
|
@ -54,6 +54,7 @@ do { \
|
|||
|
||||
#define NUM_FL_PTE 4096
|
||||
#define NUM_SL_PTE 256
|
||||
#define NUM_TEX_CLASS 8
|
||||
|
||||
/* First-level page table bits */
|
||||
#define FL_BASE_MASK 0xFFFFFC00
|
||||
|
@ -63,6 +64,9 @@ do { \
|
|||
#define FL_AP_WRITE (1 << 10)
|
||||
#define FL_AP_READ (1 << 11)
|
||||
#define FL_SHARED (1 << 16)
|
||||
#define FL_BUFFERABLE (1 << 2)
|
||||
#define FL_CACHEABLE (1 << 3)
|
||||
#define FL_TEX0 (1 << 12)
|
||||
#define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20)
|
||||
|
||||
/* Second-level page table bits */
|
||||
|
@ -73,8 +77,20 @@ do { \
|
|||
#define SL_AP0 (1 << 4)
|
||||
#define SL_AP1 (2 << 4)
|
||||
#define SL_SHARED (1 << 10)
|
||||
#define SL_BUFFERABLE (1 << 2)
|
||||
#define SL_CACHEABLE (1 << 3)
|
||||
#define SL_TEX0 (1 << 6)
|
||||
#define SL_OFFSET(va) (((va) & 0xFF000) >> 12)
|
||||
|
||||
/* Memory type and cache policy attributes */
|
||||
#define MT_SO 0
|
||||
#define MT_DEV 1
|
||||
#define MT_NORMAL 2
|
||||
#define CP_NONCACHED 0
|
||||
#define CP_WB_WA 1
|
||||
#define CP_WT 2
|
||||
#define CP_WB_NWA 3
|
||||
|
||||
/* Global register setters / getters */
|
||||
#define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v))
|
||||
#define SET_CBACR_N(b, N, v) SET_GLOBAL_REG_N(CBACR_N, N, (b), (v))
|
||||
|
@ -706,7 +722,9 @@ do { \
|
|||
#define GET_OCPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC5)
|
||||
#define GET_OCPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC6)
|
||||
#define GET_OCPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC7)
|
||||
|
||||
#define NMRR_ICP(nmrr, n) (((nmrr) & (3 << ((n) * 2))) >> ((n) * 2))
|
||||
#define NMRR_OCP(nmrr, n) (((nmrr) & (3 << ((n) * 2 + 16))) >> \
|
||||
((n) * 2 + 16))
|
||||
|
||||
/* PAR */
|
||||
#define GET_FAULT(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT)
|
||||
|
@ -750,6 +768,8 @@ do { \
|
|||
#define GET_NOS5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS5)
|
||||
#define GET_NOS6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS6)
|
||||
#define GET_NOS7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS7)
|
||||
#define PRRR_NOS(prrr, n) ((prrr) & (1 << ((n) + 24)) ? 1 : 0)
|
||||
#define PRRR_MT(prrr, n) ((((prrr) & (3 << ((n) * 2))) >> ((n) * 2)))
|
||||
|
||||
|
||||
/* RESUME */
|
||||
|
|
|
@ -237,7 +237,12 @@
|
|||
#define GSBI11_QUP_IRQ (GIC_SPI_START + 194)
|
||||
#define INT_UART12DM_IRQ (GIC_SPI_START + 195)
|
||||
#define GSBI12_QUP_IRQ (GIC_SPI_START + 196)
|
||||
/*SPI 197 to 216 arent used in 8x60*/
|
||||
|
||||
/*SPI 197 to 209 arent used in 8x60*/
|
||||
#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210)
|
||||
#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211)
|
||||
|
||||
/*SPI 212 to 216 arent used in 8x60*/
|
||||
#define SMPSS_SPARE_1 (GIC_SPI_START + 217)
|
||||
#define SMPSS_SPARE_2 (GIC_SPI_START + 218)
|
||||
#define SMPSS_SPARE_3 (GIC_SPI_START + 219)
|
||||
|
|
|
@ -119,4 +119,7 @@
|
|||
#define MSM_AD5_PHYS 0xA7000000
|
||||
#define MSM_AD5_SIZE (SZ_1M*13)
|
||||
|
||||
#define MSM_HSUSB_PHYS 0xA3600000
|
||||
#define MSM_HSUSB_SIZE SZ_1K
|
||||
|
||||
#endif
|
||||
|
|
|
@ -98,4 +98,7 @@
|
|||
#define MSM_IOMMU_GFX2D0_PHYS 0x07D00000
|
||||
#define MSM_IOMMU_GFX2D0_SIZE SZ_1M
|
||||
|
||||
#define MSM_IOMMU_GFX2D1_PHYS 0x07E00000
|
||||
#define MSM_IOMMU_GFX2D1_SIZE SZ_1M
|
||||
|
||||
#endif
|
||||
|
|
|
@ -163,3 +163,4 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
|
|||
return __arm_ioremap_caller(phys_addr, size, mtype,
|
||||
__builtin_return_address(0));
|
||||
}
|
||||
EXPORT_SYMBOL(__msm_ioremap);
|
||||
|
|
|
@ -33,6 +33,16 @@
|
|||
#include <mach/iommu_hw-8xxx.h>
|
||||
#include <mach/iommu.h>
|
||||
|
||||
#define MRC(reg, processor, op1, crn, crm, op2) \
|
||||
__asm__ __volatile__ ( \
|
||||
" mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \
|
||||
: "=r" (reg))
|
||||
|
||||
#define RCP15_PRRR(reg) MRC(reg, p15, 0, c10, c2, 0)
|
||||
#define RCP15_NMRR(reg) MRC(reg, p15, 0, c10, c2, 1)
|
||||
|
||||
static int msm_iommu_tex_class[4];
|
||||
|
||||
DEFINE_SPINLOCK(msm_iommu_lock);
|
||||
|
||||
struct msm_priv {
|
||||
|
@ -40,23 +50,26 @@ struct msm_priv {
|
|||
struct list_head list_attached;
|
||||
};
|
||||
|
||||
static void __flush_iotlb(struct iommu_domain *domain)
|
||||
static int __flush_iotlb(struct iommu_domain *domain)
|
||||
{
|
||||
struct msm_priv *priv = domain->priv;
|
||||
struct msm_iommu_drvdata *iommu_drvdata;
|
||||
struct msm_iommu_ctx_drvdata *ctx_drvdata;
|
||||
|
||||
int ret = 0;
|
||||
#ifndef CONFIG_IOMMU_PGTABLES_L2
|
||||
unsigned long *fl_table = priv->pgtable;
|
||||
int i;
|
||||
|
||||
dmac_flush_range(fl_table, fl_table + SZ_16K);
|
||||
if (!list_empty(&priv->list_attached)) {
|
||||
dmac_flush_range(fl_table, fl_table + SZ_16K);
|
||||
|
||||
for (i = 0; i < NUM_FL_PTE; i++)
|
||||
if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) {
|
||||
void *sl_table = __va(fl_table[i] & FL_BASE_MASK);
|
||||
dmac_flush_range(sl_table, sl_table + SZ_4K);
|
||||
}
|
||||
for (i = 0; i < NUM_FL_PTE; i++)
|
||||
if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) {
|
||||
void *sl_table = __va(fl_table[i] &
|
||||
FL_BASE_MASK);
|
||||
dmac_flush_range(sl_table, sl_table + SZ_4K);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) {
|
||||
|
@ -66,6 +79,8 @@ static void __flush_iotlb(struct iommu_domain *domain)
|
|||
iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
|
||||
SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __reset_context(void __iomem *base, int ctx)
|
||||
|
@ -95,6 +110,7 @@ static void __reset_context(void __iomem *base, int ctx)
|
|||
|
||||
static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable)
|
||||
{
|
||||
unsigned int prrr, nmrr;
|
||||
__reset_context(base, ctx);
|
||||
|
||||
/* Set up HTW mode */
|
||||
|
@ -127,11 +143,11 @@ static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable)
|
|||
/* Turn on TEX Remap */
|
||||
SET_TRE(base, ctx, 1);
|
||||
|
||||
/* Do not configure PRRR / NMRR on the IOMMU for now. We will assume
|
||||
* TEX class 0 for everything until attributes are properly worked out
|
||||
*/
|
||||
SET_PRRR(base, ctx, 0);
|
||||
SET_NMRR(base, ctx, 0);
|
||||
/* Set TEX remap attributes */
|
||||
RCP15_PRRR(prrr);
|
||||
RCP15_NMRR(nmrr);
|
||||
SET_PRRR(base, ctx, prrr);
|
||||
SET_NMRR(base, ctx, nmrr);
|
||||
|
||||
/* Turn on BFB prefetch */
|
||||
SET_BFBDFE(base, ctx, 1);
|
||||
|
@ -238,6 +254,11 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
|
|||
goto fail;
|
||||
}
|
||||
|
||||
if (!list_empty(&ctx_drvdata->attached_elm)) {
|
||||
ret = -EBUSY;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
list_for_each_entry(tmp_drvdata, &priv->list_attached, attached_elm)
|
||||
if (tmp_drvdata == ctx_drvdata) {
|
||||
ret = -EBUSY;
|
||||
|
@ -248,7 +269,7 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
|
|||
__pa(priv->pgtable));
|
||||
|
||||
list_add(&(ctx_drvdata->attached_elm), &priv->list_attached);
|
||||
__flush_iotlb(domain);
|
||||
ret = __flush_iotlb(domain);
|
||||
|
||||
fail:
|
||||
spin_unlock_irqrestore(&msm_iommu_lock, flags);
|
||||
|
@ -263,6 +284,7 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain,
|
|||
struct msm_iommu_drvdata *iommu_drvdata;
|
||||
struct msm_iommu_ctx_drvdata *ctx_drvdata;
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
spin_lock_irqsave(&msm_iommu_lock, flags);
|
||||
priv = domain->priv;
|
||||
|
@ -277,7 +299,10 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain,
|
|||
if (!iommu_drvdata || !ctx_drvdata || !ctx_dev)
|
||||
goto fail;
|
||||
|
||||
__flush_iotlb(domain);
|
||||
ret = __flush_iotlb(domain);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
__reset_context(iommu_drvdata->base, ctx_dev->num);
|
||||
list_del_init(&ctx_drvdata->attached_elm);
|
||||
|
||||
|
@ -296,12 +321,21 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
|
|||
unsigned long *sl_table;
|
||||
unsigned long *sl_pte;
|
||||
unsigned long sl_offset;
|
||||
unsigned int pgprot;
|
||||
size_t len = 0x1000UL << order;
|
||||
int ret = 0;
|
||||
int ret = 0, tex, sh;
|
||||
|
||||
spin_lock_irqsave(&msm_iommu_lock, flags);
|
||||
priv = domain->priv;
|
||||
|
||||
sh = (prot & MSM_IOMMU_ATTR_SH) ? 1 : 0;
|
||||
tex = msm_iommu_tex_class[prot & MSM_IOMMU_CP_MASK];
|
||||
|
||||
if (tex < 0 || tex > NUM_TEX_CLASS - 1) {
|
||||
ret = -EINVAL;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
priv = domain->priv;
|
||||
if (!priv) {
|
||||
ret = -EINVAL;
|
||||
goto fail;
|
||||
|
@ -322,6 +356,18 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
|
|||
goto fail;
|
||||
}
|
||||
|
||||
if (len == SZ_16M || len == SZ_1M) {
|
||||
pgprot = sh ? FL_SHARED : 0;
|
||||
pgprot |= tex & 0x01 ? FL_BUFFERABLE : 0;
|
||||
pgprot |= tex & 0x02 ? FL_CACHEABLE : 0;
|
||||
pgprot |= tex & 0x04 ? FL_TEX0 : 0;
|
||||
} else {
|
||||
pgprot = sh ? SL_SHARED : 0;
|
||||
pgprot |= tex & 0x01 ? SL_BUFFERABLE : 0;
|
||||
pgprot |= tex & 0x02 ? SL_CACHEABLE : 0;
|
||||
pgprot |= tex & 0x04 ? SL_TEX0 : 0;
|
||||
}
|
||||
|
||||
fl_offset = FL_OFFSET(va); /* Upper 12 bits */
|
||||
fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */
|
||||
|
||||
|
@ -330,17 +376,17 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
|
|||
for (i = 0; i < 16; i++)
|
||||
*(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION |
|
||||
FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT |
|
||||
FL_SHARED;
|
||||
FL_SHARED | pgprot;
|
||||
}
|
||||
|
||||
if (len == SZ_1M)
|
||||
*fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE |
|
||||
FL_TYPE_SECT | FL_SHARED;
|
||||
FL_TYPE_SECT | FL_SHARED | pgprot;
|
||||
|
||||
/* Need a 2nd level table */
|
||||
if ((len == SZ_4K || len == SZ_64K) && (*fl_pte) == 0) {
|
||||
unsigned long *sl;
|
||||
sl = (unsigned long *) __get_free_pages(GFP_KERNEL,
|
||||
sl = (unsigned long *) __get_free_pages(GFP_ATOMIC,
|
||||
get_order(SZ_4K));
|
||||
|
||||
if (!sl) {
|
||||
|
@ -360,17 +406,17 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
|
|||
|
||||
if (len == SZ_4K)
|
||||
*sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 |
|
||||
SL_SHARED | SL_TYPE_SMALL;
|
||||
SL_SHARED | SL_TYPE_SMALL | pgprot;
|
||||
|
||||
if (len == SZ_64K) {
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 16; i++)
|
||||
*(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 |
|
||||
SL_AP1 | SL_SHARED | SL_TYPE_LARGE;
|
||||
SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot;
|
||||
}
|
||||
|
||||
__flush_iotlb(domain);
|
||||
ret = __flush_iotlb(domain);
|
||||
fail:
|
||||
spin_unlock_irqrestore(&msm_iommu_lock, flags);
|
||||
return ret;
|
||||
|
@ -455,7 +501,7 @@ static int msm_iommu_unmap(struct iommu_domain *domain, unsigned long va,
|
|||
}
|
||||
}
|
||||
|
||||
__flush_iotlb(domain);
|
||||
ret = __flush_iotlb(domain);
|
||||
fail:
|
||||
spin_unlock_irqrestore(&msm_iommu_lock, flags);
|
||||
return ret;
|
||||
|
@ -490,9 +536,6 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
|
|||
SET_CTX_TLBIALL(base, ctx, 0);
|
||||
SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT);
|
||||
|
||||
if (GET_FAULT(base, ctx))
|
||||
goto fail;
|
||||
|
||||
par = GET_PAR(base, ctx);
|
||||
|
||||
/* We are dealing with a supersection */
|
||||
|
@ -501,6 +544,9 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
|
|||
else /* Upper 20 bits from PAR, lower 12 from VA */
|
||||
ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
|
||||
|
||||
if (GET_FAULT(base, ctx))
|
||||
ret = 0;
|
||||
|
||||
fail:
|
||||
spin_unlock_irqrestore(&msm_iommu_lock, flags);
|
||||
return ret;
|
||||
|
@ -543,8 +589,8 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
|
|||
{
|
||||
struct msm_iommu_drvdata *drvdata = dev_id;
|
||||
void __iomem *base;
|
||||
unsigned int fsr = 0;
|
||||
int ncb = 0, i = 0;
|
||||
unsigned int fsr;
|
||||
int ncb, i;
|
||||
|
||||
spin_lock(&msm_iommu_lock);
|
||||
|
||||
|
@ -555,7 +601,6 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
|
|||
|
||||
base = drvdata->base;
|
||||
|
||||
pr_err("===== WOAH! =====\n");
|
||||
pr_err("Unexpected IOMMU page fault!\n");
|
||||
pr_err("base = %08x\n", (unsigned int) base);
|
||||
|
||||
|
@ -585,8 +630,47 @@ static struct iommu_ops msm_iommu_ops = {
|
|||
.domain_has_cap = msm_iommu_domain_has_cap
|
||||
};
|
||||
|
||||
static int msm_iommu_init(void)
|
||||
static int __init get_tex_class(int icp, int ocp, int mt, int nos)
|
||||
{
|
||||
int i = 0;
|
||||
unsigned int prrr = 0;
|
||||
unsigned int nmrr = 0;
|
||||
int c_icp, c_ocp, c_mt, c_nos;
|
||||
|
||||
RCP15_PRRR(prrr);
|
||||
RCP15_NMRR(nmrr);
|
||||
|
||||
for (i = 0; i < NUM_TEX_CLASS; i++) {
|
||||
c_nos = PRRR_NOS(prrr, i);
|
||||
c_mt = PRRR_MT(prrr, i);
|
||||
c_icp = NMRR_ICP(nmrr, i);
|
||||
c_ocp = NMRR_OCP(nmrr, i);
|
||||
|
||||
if (icp == c_icp && ocp == c_ocp && c_mt == mt && c_nos == nos)
|
||||
return i;
|
||||
}
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static void __init setup_iommu_tex_classes(void)
|
||||
{
|
||||
msm_iommu_tex_class[MSM_IOMMU_ATTR_NONCACHED] =
|
||||
get_tex_class(CP_NONCACHED, CP_NONCACHED, MT_NORMAL, 1);
|
||||
|
||||
msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_WA] =
|
||||
get_tex_class(CP_WB_WA, CP_WB_WA, MT_NORMAL, 1);
|
||||
|
||||
msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_NWA] =
|
||||
get_tex_class(CP_WB_NWA, CP_WB_NWA, MT_NORMAL, 1);
|
||||
|
||||
msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WT] =
|
||||
get_tex_class(CP_WT, CP_WT, MT_NORMAL, 1);
|
||||
}
|
||||
|
||||
static int __init msm_iommu_init(void)
|
||||
{
|
||||
setup_iommu_tex_classes();
|
||||
register_iommu(&msm_iommu_ops);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -346,7 +346,7 @@ static struct platform_driver msm_iommu_ctx_driver = {
|
|||
.remove = msm_iommu_ctx_remove,
|
||||
};
|
||||
|
||||
static int msm_iommu_driver_init(void)
|
||||
static int __init msm_iommu_driver_init(void)
|
||||
{
|
||||
int ret;
|
||||
ret = platform_driver_register(&msm_iommu_driver);
|
||||
|
@ -365,7 +365,7 @@ error:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void msm_iommu_driver_exit(void)
|
||||
static void __exit msm_iommu_driver_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&msm_iommu_ctx_driver);
|
||||
platform_driver_unregister(&msm_iommu_driver);
|
||||
|
|
|
@ -40,9 +40,6 @@ static struct sirc_cascade_regs sirc_reg_table[] = {
|
|||
}
|
||||
};
|
||||
|
||||
static unsigned int save_type;
|
||||
static unsigned int save_polarity;
|
||||
|
||||
/* Mask off the given interrupt. Keep the int_enable mask in sync with
|
||||
the enable reg, so it can be restored after power collapse. */
|
||||
static void sirc_irq_mask(unsigned int irq)
|
||||
|
|
|
@ -14,6 +14,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/fs.h>
|
||||
|
@ -89,7 +91,7 @@ static void smd_diag(void)
|
|||
x = smem_find(ID_DIAG_ERR_MSG, SZ_DIAG_ERR_MSG);
|
||||
if (x != 0) {
|
||||
x[SZ_DIAG_ERR_MSG - 1] = 0;
|
||||
pr_info("smem: DIAG '%s'\n", x);
|
||||
pr_debug("DIAG '%s'\n", x);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -312,7 +314,7 @@ static void smd_state_change(struct smd_channel *ch,
|
|||
{
|
||||
ch->last_state = next;
|
||||
|
||||
pr_info("SMD: ch %d %d -> %d\n", ch->n, last, next);
|
||||
pr_debug("ch %d %d -> %d\n", ch->n, last, next);
|
||||
|
||||
switch (next) {
|
||||
case SMD_SS_OPENING:
|
||||
|
@ -601,7 +603,7 @@ static int smd_alloc_channel(const char *name, uint32_t cid, uint32_t type)
|
|||
ch->pdev.name = ch->name;
|
||||
ch->pdev.id = -1;
|
||||
|
||||
pr_info("smd_alloc_channel() cid=%02d size=%05d '%s'\n",
|
||||
pr_debug("smd_alloc_channel() cid=%02d size=%05d '%s'\n",
|
||||
ch->n, ch->fifo_size, ch->name);
|
||||
|
||||
mutex_lock(&smd_creation_mutex);
|
||||
|
@ -621,7 +623,7 @@ static void smd_channel_probe_worker(struct work_struct *work)
|
|||
|
||||
shared = smem_find(ID_CH_ALLOC_TBL, sizeof(*shared) * 64);
|
||||
if (!shared) {
|
||||
pr_err("smd: cannot find allocation table\n");
|
||||
pr_err("cannot find allocation table\n");
|
||||
return;
|
||||
}
|
||||
for (n = 0; n < 64; n++) {
|
||||
|
@ -725,8 +727,6 @@ int smd_close(smd_channel_t *ch)
|
|||
{
|
||||
unsigned long flags;
|
||||
|
||||
pr_info("smd_close(%p)\n", ch);
|
||||
|
||||
if (ch == 0)
|
||||
return -1;
|
||||
|
||||
|
@ -939,7 +939,6 @@ int smsm_set_sleep_duration(uint32_t delay)
|
|||
int smd_core_init(void)
|
||||
{
|
||||
int r;
|
||||
pr_info("smd_core_init()\n");
|
||||
|
||||
/* wait for essential items to be initialized */
|
||||
for (;;) {
|
||||
|
@ -992,15 +991,11 @@ int smd_core_init(void)
|
|||
smsm_change_state(SMSM_STATE_APPS_DEM, ~0, 0);
|
||||
#endif
|
||||
|
||||
pr_info("smd_core_init() done\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __devinit msm_smd_probe(struct platform_device *pdev)
|
||||
{
|
||||
pr_info("smd_init()\n");
|
||||
|
||||
/*
|
||||
* If we haven't waited for the ARM9 to boot up till now,
|
||||
* then we need to wait here. Otherwise this should just
|
||||
|
|
|
@ -270,8 +270,10 @@ void smsm_print_sleep_info(void)
|
|||
{
|
||||
unsigned long flags;
|
||||
uint32_t *ptr;
|
||||
#ifndef CONFIG_ARCH_MSM_SCORPION
|
||||
struct tramp_gpio_smem *gpio;
|
||||
struct smsm_interrupt_info *int_info;
|
||||
#endif
|
||||
|
||||
|
||||
spin_lock_irqsave(&smem_lock, flags);
|
||||
|
|
|
@ -44,6 +44,7 @@
|
|||
#include <mach/mmc.h>
|
||||
#include <mach/msm_iomap.h>
|
||||
#include <mach/dma.h>
|
||||
#include <mach/clk.h>
|
||||
|
||||
#include "msm_sdcc.h"
|
||||
|
||||
|
@ -126,6 +127,40 @@ static void
|
|||
msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
|
||||
u32 c);
|
||||
|
||||
static void msmsdcc_reset_and_restore(struct msmsdcc_host *host)
|
||||
{
|
||||
u32 mci_clk = 0;
|
||||
u32 mci_mask0 = 0;
|
||||
int ret = 0;
|
||||
|
||||
/* Save the controller state */
|
||||
mci_clk = readl(host->base + MMCICLOCK);
|
||||
mci_mask0 = readl(host->base + MMCIMASK0);
|
||||
|
||||
/* Reset the controller */
|
||||
ret = clk_reset(host->clk, CLK_RESET_ASSERT);
|
||||
if (ret)
|
||||
pr_err("%s: Clock assert failed at %u Hz with err %d\n",
|
||||
mmc_hostname(host->mmc), host->clk_rate, ret);
|
||||
|
||||
ret = clk_reset(host->clk, CLK_RESET_DEASSERT);
|
||||
if (ret)
|
||||
pr_err("%s: Clock deassert failed at %u Hz with err %d\n",
|
||||
mmc_hostname(host->mmc), host->clk_rate, ret);
|
||||
|
||||
pr_info("%s: Controller has been re-initialiazed\n",
|
||||
mmc_hostname(host->mmc));
|
||||
|
||||
/* Restore the contoller state */
|
||||
writel(host->pwr, host->base + MMCIPOWER);
|
||||
writel(mci_clk, host->base + MMCICLOCK);
|
||||
writel(mci_mask0, host->base + MMCIMASK0);
|
||||
ret = clk_set_rate(host->clk, host->clk_rate);
|
||||
if (ret)
|
||||
pr_err("%s: Failed to set clk rate %u Hz (%d)\n",
|
||||
mmc_hostname(host->mmc), host->clk_rate, ret);
|
||||
}
|
||||
|
||||
static void
|
||||
msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
|
||||
{
|
||||
|
@ -155,7 +190,7 @@ static void
|
|||
msmsdcc_stop_data(struct msmsdcc_host *host)
|
||||
{
|
||||
host->curr.data = NULL;
|
||||
host->curr.got_dataend = host->curr.got_datablkend = 0;
|
||||
host->curr.got_dataend = 0;
|
||||
}
|
||||
|
||||
uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host)
|
||||
|
@ -189,42 +224,42 @@ msmsdcc_dma_exec_func(struct msm_dmov_cmd *cmd)
|
|||
}
|
||||
|
||||
static void
|
||||
msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
|
||||
unsigned int result,
|
||||
struct msm_dmov_errdata *err)
|
||||
msmsdcc_dma_complete_tlet(unsigned long data)
|
||||
{
|
||||
struct msmsdcc_dma_data *dma_data =
|
||||
container_of(cmd, struct msmsdcc_dma_data, hdr);
|
||||
struct msmsdcc_host *host = dma_data->host;
|
||||
struct msmsdcc_host *host = (struct msmsdcc_host *)data;
|
||||
unsigned long flags;
|
||||
struct mmc_request *mrq;
|
||||
struct msm_dmov_errdata err;
|
||||
|
||||
spin_lock_irqsave(&host->lock, flags);
|
||||
host->dma.active = 0;
|
||||
|
||||
err = host->dma.err;
|
||||
mrq = host->curr.mrq;
|
||||
BUG_ON(!mrq);
|
||||
WARN_ON(!mrq->data);
|
||||
|
||||
if (!(result & DMOV_RSLT_VALID)) {
|
||||
if (!(host->dma.result & DMOV_RSLT_VALID)) {
|
||||
pr_err("msmsdcc: Invalid DataMover result\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (result & DMOV_RSLT_DONE) {
|
||||
if (host->dma.result & DMOV_RSLT_DONE) {
|
||||
host->curr.data_xfered = host->curr.xfer_size;
|
||||
} else {
|
||||
/* Error or flush */
|
||||
if (result & DMOV_RSLT_ERROR)
|
||||
if (host->dma.result & DMOV_RSLT_ERROR)
|
||||
pr_err("%s: DMA error (0x%.8x)\n",
|
||||
mmc_hostname(host->mmc), result);
|
||||
if (result & DMOV_RSLT_FLUSH)
|
||||
mmc_hostname(host->mmc), host->dma.result);
|
||||
if (host->dma.result & DMOV_RSLT_FLUSH)
|
||||
pr_err("%s: DMA channel flushed (0x%.8x)\n",
|
||||
mmc_hostname(host->mmc), result);
|
||||
if (err)
|
||||
pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n",
|
||||
err->flush[0], err->flush[1], err->flush[2],
|
||||
err->flush[3], err->flush[4], err->flush[5]);
|
||||
mmc_hostname(host->mmc), host->dma.result);
|
||||
|
||||
pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n",
|
||||
err.flush[0], err.flush[1], err.flush[2],
|
||||
err.flush[3], err.flush[4], err.flush[5]);
|
||||
|
||||
msmsdcc_reset_and_restore(host);
|
||||
if (!mrq->data->error)
|
||||
mrq->data->error = -EIO;
|
||||
}
|
||||
|
@ -242,8 +277,7 @@ msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
|
|||
host->dma.sg = NULL;
|
||||
host->dma.busy = 0;
|
||||
|
||||
if ((host->curr.got_dataend && host->curr.got_datablkend)
|
||||
|| mrq->data->error) {
|
||||
if (host->curr.got_dataend || mrq->data->error) {
|
||||
|
||||
/*
|
||||
* If we've already gotten our DATAEND / DATABLKEND
|
||||
|
@ -273,6 +307,22 @@ out:
|
|||
return;
|
||||
}
|
||||
|
||||
static void
|
||||
msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
|
||||
unsigned int result,
|
||||
struct msm_dmov_errdata *err)
|
||||
{
|
||||
struct msmsdcc_dma_data *dma_data =
|
||||
container_of(cmd, struct msmsdcc_dma_data, hdr);
|
||||
struct msmsdcc_host *host = dma_data->host;
|
||||
|
||||
dma_data->result = result;
|
||||
if (err)
|
||||
memcpy(&dma_data->err, err, sizeof(struct msm_dmov_errdata));
|
||||
|
||||
tasklet_schedule(&host->dma_tlet);
|
||||
}
|
||||
|
||||
static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data)
|
||||
{
|
||||
if (host->dma.channel == -1)
|
||||
|
@ -424,6 +474,11 @@ msmsdcc_start_command_deferred(struct msmsdcc_host *host,
|
|||
(cmd->opcode == 53))
|
||||
*c |= MCI_CSPM_DATCMD;
|
||||
|
||||
if (host->prog_scan && (cmd->opcode == 12)) {
|
||||
*c |= MCI_CPSM_PROGENA;
|
||||
host->prog_enable = true;
|
||||
}
|
||||
|
||||
if (cmd == cmd->mrq->stop)
|
||||
*c |= MCI_CSPM_MCIABORT;
|
||||
|
||||
|
@ -450,7 +505,6 @@ msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data,
|
|||
host->curr.xfer_remain = host->curr.xfer_size;
|
||||
host->curr.data_xfered = 0;
|
||||
host->curr.got_dataend = 0;
|
||||
host->curr.got_datablkend = 0;
|
||||
|
||||
memset(&host->pio, 0, sizeof(host->pio));
|
||||
|
||||
|
@ -494,6 +548,8 @@ msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data,
|
|||
host->cmd_c = c;
|
||||
}
|
||||
msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr);
|
||||
if (data->flags & MMC_DATA_WRITE)
|
||||
host->prog_scan = true;
|
||||
} else {
|
||||
msmsdcc_writel(host, timeout, MMCIDATATIMER);
|
||||
|
||||
|
@ -555,6 +611,9 @@ msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain)
|
|||
uint32_t *ptr = (uint32_t *) buffer;
|
||||
int count = 0;
|
||||
|
||||
if (remain % 4)
|
||||
remain = ((remain >> 2) + 1) << 2;
|
||||
|
||||
while (msmsdcc_readl(host, MMCISTATUS) & MCI_RXDATAAVLBL) {
|
||||
*ptr = msmsdcc_readl(host, MMCIFIFO + (count % MCI_FIFOSIZE));
|
||||
ptr++;
|
||||
|
@ -575,13 +634,14 @@ msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer,
|
|||
char *ptr = buffer;
|
||||
|
||||
do {
|
||||
unsigned int count, maxcnt;
|
||||
unsigned int count, maxcnt, sz;
|
||||
|
||||
maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE :
|
||||
MCI_FIFOHALFSIZE;
|
||||
count = min(remain, maxcnt);
|
||||
|
||||
writesl(base + MMCIFIFO, ptr, count >> 2);
|
||||
sz = count % 4 ? (count >> 2) + 1 : (count >> 2);
|
||||
writesl(base + MMCIFIFO, ptr, sz);
|
||||
ptr += count;
|
||||
remain -= count;
|
||||
|
||||
|
@ -702,10 +762,26 @@ static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
|
|||
msm_dmov_stop_cmd(host->dma.channel,
|
||||
&host->dma.hdr, 0);
|
||||
else if (host->curr.data) { /* Non DMA */
|
||||
msmsdcc_reset_and_restore(host);
|
||||
msmsdcc_stop_data(host);
|
||||
msmsdcc_request_end(host, cmd->mrq);
|
||||
} else /* host->data == NULL */
|
||||
msmsdcc_request_end(host, cmd->mrq);
|
||||
} else { /* host->data == NULL */
|
||||
if (!cmd->error && host->prog_enable) {
|
||||
if (status & MCI_PROGDONE) {
|
||||
host->prog_scan = false;
|
||||
host->prog_enable = false;
|
||||
msmsdcc_request_end(host, cmd->mrq);
|
||||
} else {
|
||||
host->curr.cmd = cmd;
|
||||
}
|
||||
} else {
|
||||
if (host->prog_enable) {
|
||||
host->prog_scan = false;
|
||||
host->prog_enable = false;
|
||||
}
|
||||
msmsdcc_request_end(host, cmd->mrq);
|
||||
}
|
||||
}
|
||||
} else if (cmd->data)
|
||||
if (!(cmd->data->flags & MMC_DATA_READ))
|
||||
msmsdcc_start_data(host, cmd->data,
|
||||
|
@ -719,7 +795,7 @@ msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
|
|||
struct mmc_data *data = host->curr.data;
|
||||
|
||||
if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL |
|
||||
MCI_CMDTIMEOUT) && host->curr.cmd) {
|
||||
MCI_CMDTIMEOUT | MCI_PROGDONE) && host->curr.cmd) {
|
||||
msmsdcc_do_cmdirq(host, status);
|
||||
}
|
||||
|
||||
|
@ -735,6 +811,7 @@ msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
|
|||
msm_dmov_stop_cmd(host->dma.channel,
|
||||
&host->dma.hdr, 0);
|
||||
else {
|
||||
msmsdcc_reset_and_restore(host);
|
||||
if (host->curr.data)
|
||||
msmsdcc_stop_data(host);
|
||||
if (!data->stop)
|
||||
|
@ -748,14 +825,10 @@ msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
|
|||
if (!host->curr.got_dataend && (status & MCI_DATAEND))
|
||||
host->curr.got_dataend = 1;
|
||||
|
||||
if (!host->curr.got_datablkend && (status & MCI_DATABLOCKEND))
|
||||
host->curr.got_datablkend = 1;
|
||||
|
||||
/*
|
||||
* If DMA is still in progress, we complete via the completion handler
|
||||
*/
|
||||
if (host->curr.got_dataend && host->curr.got_datablkend &&
|
||||
!host->dma.busy) {
|
||||
if (host->curr.got_dataend && !host->dma.busy) {
|
||||
/*
|
||||
* There appears to be an issue in the controller where
|
||||
* if you request a small block transfer (< fifo size),
|
||||
|
@ -792,8 +865,7 @@ msmsdcc_irq(int irq, void *dev_id)
|
|||
|
||||
do {
|
||||
status = msmsdcc_readl(host, MMCISTATUS);
|
||||
status &= (msmsdcc_readl(host, MMCIMASK0) |
|
||||
MCI_DATABLOCKENDMASK);
|
||||
status &= msmsdcc_readl(host, MMCIMASK0);
|
||||
msmsdcc_writel(host, status, MMCICLEAR);
|
||||
|
||||
if (status & MCI_SDIOINTR)
|
||||
|
@ -1118,6 +1190,9 @@ msmsdcc_probe(struct platform_device *pdev)
|
|||
host->dmares = dmares;
|
||||
spin_lock_init(&host->lock);
|
||||
|
||||
tasklet_init(&host->dma_tlet, msmsdcc_dma_complete_tlet,
|
||||
(unsigned long)host);
|
||||
|
||||
/*
|
||||
* Setup DMA
|
||||
*/
|
||||
|
|
|
@ -138,7 +138,7 @@
|
|||
#define MCI_IRQENABLE \
|
||||
(MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \
|
||||
MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
|
||||
MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATAENDMASK)
|
||||
MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATAENDMASK|MCI_PROGDONEMASK)
|
||||
|
||||
/*
|
||||
* The size of the FIFO in bytes.
|
||||
|
@ -172,6 +172,8 @@ struct msmsdcc_dma_data {
|
|||
struct msmsdcc_host *host;
|
||||
int busy; /* Set if DM is busy */
|
||||
int active;
|
||||
unsigned int result;
|
||||
struct msm_dmov_errdata err;
|
||||
};
|
||||
|
||||
struct msmsdcc_pio_data {
|
||||
|
@ -188,7 +190,6 @@ struct msmsdcc_curr_req {
|
|||
unsigned int xfer_remain; /* Bytes remaining to send */
|
||||
unsigned int data_xfered; /* Bytes acked by BLKEND irq */
|
||||
int got_dataend;
|
||||
int got_datablkend;
|
||||
int user_pages;
|
||||
};
|
||||
|
||||
|
@ -235,6 +236,7 @@ struct msmsdcc_host {
|
|||
int cmdpoll;
|
||||
struct msmsdcc_stats stats;
|
||||
|
||||
struct tasklet_struct dma_tlet;
|
||||
/* Command parameters */
|
||||
unsigned int cmd_timeout;
|
||||
unsigned int cmd_pio_irqmask;
|
||||
|
@ -242,6 +244,8 @@ struct msmsdcc_host {
|
|||
struct mmc_command *cmd_cmd;
|
||||
u32 cmd_c;
|
||||
|
||||
bool prog_scan;
|
||||
bool prog_enable;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -686,7 +686,7 @@ static int __init msm_serial_probe(struct platform_device *pdev)
|
|||
msm_port = UART_TO_MSM(port);
|
||||
|
||||
msm_port->clk = clk_get(&pdev->dev, "uart_clk");
|
||||
if (unlikely(IS_ERR(msm_port->clk)))
|
||||
if (IS_ERR(msm_port->clk))
|
||||
return PTR_ERR(msm_port->clk);
|
||||
port->uartclk = clk_get_rate(msm_port->clk);
|
||||
printk(KERN_INFO "uartclk = %d\n", port->uartclk);
|
||||
|
|
Loading…
Reference in New Issue