arm64 perf updates for 4.7
- Support for the PMU in Broadcom's Vulcan CPU - Dynamic event detection using the PMCEIDn_EL0 ID registers -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCgAGBQJXNhyFAAoJELescNyEwWM0A0gIAL52VQid16PvLgEO4g6mzv5B S1ef/y45342R/DYczcUSFboMPuqYSxZ/i7dCwpvLUKX/YjyqQrrGvvS4IYOS99Mp /OAcf8eTyzzVpJiGQetta3q20gNHGXOxd48R1zcgt+bbEax89lyHQul0A8+rPWLq RZhEI6Hcq9fb70AjXjWvDxdbbJhtDKc8BGuptygOEqc8LO3mrb1J60TclU629XOH Jn4Vdu5f6Rx8hPFdw5HXn+Vdheymphz0qj1lyGCQS4Am97bM5J/54a/A4tyHnHuQ s9Y26NIAvrktp9wCMlXGQhYL94e1rZowXCWxF98D9XrlIzYORIdf/OZ5DCS8LCA= =0ntf -----END PGP SIGNATURE----- Merge tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 perf updates from Will Deacon: "The main addition here is support for Broadcom's Vulcan core using the architected ID registers for discovering supported events. - Support for the PMU in Broadcom's Vulcan CPU - Dynamic event detection using the PMCEIDn_EL0 ID registers" * tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: perf: don't expose CHAIN event in sysfs arm64/perf: Add Broadcom Vulcan PMU support arm64/perf: Filter common events based on PMCEIDn_EL0 arm64/perf: Access pmu register using <read/write>_sys_reg arm64/perf: Define complete ARMv8 recommended implementation defined events arm64/perf: Changed events naming as per the ARM ARM arm64: dts: Add Broadcom Vulcan PMU in dts Documentation: arm64: pmu: Add Broadcom Vulcan PMU binding
This commit is contained in:
Linus Torvalds
commit
b6ae4055f4
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@ -22,10 +22,11 @@ Required properties:
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"arm,arm11mpcore-pmu"
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"arm,arm1176-pmu"
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"arm,arm1136-pmu"
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"brcm,vulcan-pmu"
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"cavium,thunder-pmu"
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"qcom,scorpion-pmu"
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"qcom,scorpion-mp-pmu"
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"qcom,krait-pmu"
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"cavium,thunder-pmu"
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- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
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interrupt (PPI) then 1 interrupt should be specified.
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@ -86,7 +86,7 @@
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */
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};
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@ -21,6 +21,7 @@
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#include <asm/irq_regs.h>
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#include <asm/perf_event.h>
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#include <asm/sysreg.h>
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#include <asm/virt.h>
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#include <linux/of.h>
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@ -33,43 +34,43 @@
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*/
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/* Required events. */
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#define ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR 0x00
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#define ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL 0x03
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#define ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS 0x04
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#define ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED 0x10
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#define ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES 0x11
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#define ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED 0x12
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#define ARMV8_PMUV3_PERFCTR_SW_INCR 0x00
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL 0x03
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE 0x04
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#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED 0x10
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#define ARMV8_PMUV3_PERFCTR_CPU_CYCLES 0x11
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#define ARMV8_PMUV3_PERFCTR_BR_PRED 0x12
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/* At least one of the following is required. */
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#define ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED 0x08
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#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x1B
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#define ARMV8_PMUV3_PERFCTR_INST_RETIRED 0x08
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#define ARMV8_PMUV3_PERFCTR_INST_SPEC 0x1B
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/* Common architectural events. */
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#define ARMV8_PMUV3_PERFCTR_MEM_READ 0x06
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#define ARMV8_PMUV3_PERFCTR_MEM_WRITE 0x07
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#define ARMV8_PMUV3_PERFCTR_LD_RETIRED 0x06
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#define ARMV8_PMUV3_PERFCTR_ST_RETIRED 0x07
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#define ARMV8_PMUV3_PERFCTR_EXC_TAKEN 0x09
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#define ARMV8_PMUV3_PERFCTR_EXC_EXECUTED 0x0A
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#define ARMV8_PMUV3_PERFCTR_CID_WRITE 0x0B
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#define ARMV8_PMUV3_PERFCTR_PC_WRITE 0x0C
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#define ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH 0x0D
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#define ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN 0x0E
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#define ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS 0x0F
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#define ARMV8_PMUV3_PERFCTR_TTBR_WRITE 0x1C
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#define ARMV8_PMUV3_PERFCTR_EXC_RETURN 0x0A
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#define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED 0x0B
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#define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED 0x0C
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#define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED 0x0D
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#define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED 0x0E
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#define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED 0x0F
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#define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED 0x1C
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#define ARMV8_PMUV3_PERFCTR_CHAIN 0x1E
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#define ARMV8_PMUV3_PERFCTR_BR_RETIRED 0x21
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/* Common microarchitectural events. */
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#define ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL 0x01
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#define ARMV8_PMUV3_PERFCTR_ITLB_REFILL 0x02
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#define ARMV8_PMUV3_PERFCTR_DTLB_REFILL 0x05
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#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL 0x01
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#define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL 0x02
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#define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL 0x05
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#define ARMV8_PMUV3_PERFCTR_MEM_ACCESS 0x13
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#define ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS 0x14
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#define ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB 0x15
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#define ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS 0x16
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#define ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL 0x17
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#define ARMV8_PMUV3_PERFCTR_L2_CACHE_WB 0x18
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#define ARMV8_PMUV3_PERFCTR_L1I_CACHE 0x14
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB 0x15
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE 0x16
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL 0x17
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB 0x18
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#define ARMV8_PMUV3_PERFCTR_BUS_ACCESS 0x19
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#define ARMV8_PMUV3_PERFCTR_MEM_ERROR 0x1A
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#define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR 0x1A
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#define ARMV8_PMUV3_PERFCTR_BUS_CYCLES 0x1D
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE 0x1F
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE 0x20
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@ -85,89 +86,182 @@
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#define ARMV8_PMUV3_PERFCTR_L3D_CACHE 0x2B
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#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB 0x2C
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#define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL 0x2D
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#define ARMV8_PMUV3_PERFCTR_L21_TLB_REFILL 0x2E
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#define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL 0x2E
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#define ARMV8_PMUV3_PERFCTR_L2D_TLB 0x2F
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#define ARMV8_PMUV3_PERFCTR_L21_TLB 0x30
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#define ARMV8_PMUV3_PERFCTR_L2I_TLB 0x30
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/* ARMv8 implementation defined event types. */
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#define ARMV8_IMPDEF_PERFCTR_L1_DCACHE_ACCESS_LD 0x40
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#define ARMV8_IMPDEF_PERFCTR_L1_DCACHE_ACCESS_ST 0x41
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#define ARMV8_IMPDEF_PERFCTR_L1_DCACHE_REFILL_LD 0x42
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#define ARMV8_IMPDEF_PERFCTR_L1_DCACHE_REFILL_ST 0x43
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#define ARMV8_IMPDEF_PERFCTR_DTLB_REFILL_LD 0x4C
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#define ARMV8_IMPDEF_PERFCTR_DTLB_REFILL_ST 0x4D
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#define ARMV8_IMPDEF_PERFCTR_DTLB_ACCESS_LD 0x4E
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#define ARMV8_IMPDEF_PERFCTR_DTLB_ACCESS_ST 0x4F
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/* ARMv8 recommended implementation defined event types */
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x40
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x41
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD 0x42
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR 0x43
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER 0x44
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER 0x45
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM 0x46
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN 0x47
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL 0x48
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#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD 0x4C
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#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR 0x4D
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#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD 0x4E
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#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR 0x4F
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD 0x50
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR 0x51
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD 0x52
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR 0x53
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM 0x56
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN 0x57
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL 0x58
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#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD 0x5C
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#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR 0x5D
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#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD 0x5E
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#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR 0x5F
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD 0x60
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR 0x61
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED 0x62
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED 0x63
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL 0x64
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH 0x65
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#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD 0x66
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#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR 0x67
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#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC 0x68
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#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC 0x69
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#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC 0x6A
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#define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC 0x6C
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#define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC 0x6D
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#define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC 0x6E
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#define ARMV8_IMPDEF_PERFCTR_STREX_SPEC 0x6F
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#define ARMV8_IMPDEF_PERFCTR_LD_SPEC 0x70
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#define ARMV8_IMPDEF_PERFCTR_ST_SPEC 0x71
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#define ARMV8_IMPDEF_PERFCTR_LDST_SPEC 0x72
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#define ARMV8_IMPDEF_PERFCTR_DP_SPEC 0x73
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#define ARMV8_IMPDEF_PERFCTR_ASE_SPEC 0x74
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#define ARMV8_IMPDEF_PERFCTR_VFP_SPEC 0x75
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#define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC 0x76
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#define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC 0x77
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#define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC 0x78
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#define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC 0x79
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#define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC 0x7A
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#define ARMV8_IMPDEF_PERFCTR_ISB_SPEC 0x7C
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#define ARMV8_IMPDEF_PERFCTR_DSB_SPEC 0x7D
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#define ARMV8_IMPDEF_PERFCTR_DMB_SPEC 0x7E
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#define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF 0x81
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#define ARMV8_IMPDEF_PERFCTR_EXC_SVC 0x82
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#define ARMV8_IMPDEF_PERFCTR_EXC_PABORT 0x83
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#define ARMV8_IMPDEF_PERFCTR_EXC_DABORT 0x84
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#define ARMV8_IMPDEF_PERFCTR_EXC_IRQ 0x86
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#define ARMV8_IMPDEF_PERFCTR_EXC_FIQ 0x87
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#define ARMV8_IMPDEF_PERFCTR_EXC_SMC 0x88
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#define ARMV8_IMPDEF_PERFCTR_EXC_HVC 0x8A
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#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT 0x8B
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#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT 0x8C
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#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER 0x8D
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#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ 0x8E
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#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ 0x8F
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#define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC 0x90
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#define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC 0x91
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD 0xA0
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR 0xA1
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD 0xA2
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR 0xA3
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM 0xA6
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN 0xA7
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL 0xA8
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/* ARMv8 Cortex-A53 specific event types. */
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#define ARMV8_A53_PERFCTR_PREFETCH_LINEFILL 0xC2
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#define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2
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/* ARMv8 Cavium ThunderX specific event types. */
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#define ARMV8_THUNDER_PERFCTR_L1_DCACHE_MISS_ST 0xE9
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#define ARMV8_THUNDER_PERFCTR_L1_DCACHE_PREF_ACCESS 0xEA
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#define ARMV8_THUNDER_PERFCTR_L1_DCACHE_PREF_MISS 0xEB
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#define ARMV8_THUNDER_PERFCTR_L1_ICACHE_PREF_ACCESS 0xEC
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#define ARMV8_THUNDER_PERFCTR_L1_ICACHE_PREF_MISS 0xED
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#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST 0xE9
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#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS 0xEA
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#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS 0xEB
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#define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS 0xEC
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#define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS 0xED
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/* PMUv3 HW events mapping. */
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static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
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PERF_MAP_ALL_UNSUPPORTED,
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
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[PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
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[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
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[PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
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[PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
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[PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
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[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
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[PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
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[PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
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};
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/* ARM Cortex-A53 HW events mapping. */
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static const unsigned armv8_a53_perf_map[PERF_COUNT_HW_MAX] = {
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PERF_MAP_ALL_UNSUPPORTED,
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
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[PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
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[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
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[PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_PC_WRITE,
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[PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
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[PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
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[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
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[PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
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||||
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
|
||||
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
|
||||
[PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
|
||||
};
|
||||
|
||||
/* ARM Cortex-A57 and Cortex-A72 events mapping. */
|
||||
static const unsigned armv8_a57_perf_map[PERF_COUNT_HW_MAX] = {
|
||||
PERF_MAP_ALL_UNSUPPORTED,
|
||||
[PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
|
||||
[PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
|
||||
[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
|
||||
[PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
|
||||
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
|
||||
[PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
|
||||
[PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
|
||||
[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
|
||||
[PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
|
||||
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
|
||||
[PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
|
||||
};
|
||||
|
||||
static const unsigned armv8_thunder_perf_map[PERF_COUNT_HW_MAX] = {
|
||||
PERF_MAP_ALL_UNSUPPORTED,
|
||||
[PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
|
||||
[PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
|
||||
[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
|
||||
[PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
|
||||
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_PC_WRITE,
|
||||
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
|
||||
[PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
|
||||
[PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
|
||||
[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
|
||||
[PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
|
||||
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
|
||||
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
|
||||
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
|
||||
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
|
||||
};
|
||||
|
||||
/* Broadcom Vulcan events mapping */
|
||||
static const unsigned armv8_vulcan_perf_map[PERF_COUNT_HW_MAX] = {
|
||||
PERF_MAP_ALL_UNSUPPORTED,
|
||||
[PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
|
||||
[PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
|
||||
[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
|
||||
[PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
|
||||
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_BR_RETIRED,
|
||||
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
|
||||
[PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
|
||||
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
|
||||
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
|
||||
};
|
||||
|
||||
static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
||||
[PERF_COUNT_HW_CACHE_OP_MAX]
|
||||
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
|
||||
PERF_CACHE_MAP_ALL_UNSUPPORTED,
|
||||
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
|
||||
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
|
||||
};
|
||||
|
||||
static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
||||
|
|
@ -175,21 +269,21 @@ static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
|||
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
|
||||
PERF_CACHE_MAP_ALL_UNSUPPORTED,
|
||||
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
|
||||
[C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREFETCH_LINEFILL,
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
|
||||
[C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
|
||||
|
||||
[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS,
|
||||
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL,
|
||||
[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
|
||||
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
|
||||
|
||||
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_ITLB_REFILL,
|
||||
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
|
||||
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
|
||||
};
|
||||
|
||||
static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
||||
|
|
@ -197,23 +291,23 @@ static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
|||
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
|
||||
PERF_CACHE_MAP_ALL_UNSUPPORTED,
|
||||
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1_DCACHE_ACCESS_LD,
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1_DCACHE_REFILL_LD,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1_DCACHE_ACCESS_ST,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1_DCACHE_REFILL_ST,
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
|
||||
|
||||
[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS,
|
||||
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL,
|
||||
[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
|
||||
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
|
||||
|
||||
[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_DTLB_REFILL_LD,
|
||||
[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_DTLB_REFILL_ST,
|
||||
[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
|
||||
[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
|
||||
|
||||
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_ITLB_REFILL,
|
||||
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
|
||||
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
|
||||
};
|
||||
|
||||
static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
||||
|
|
@ -221,67 +315,108 @@ static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
|||
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
|
||||
PERF_CACHE_MAP_ALL_UNSUPPORTED,
|
||||
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1_DCACHE_ACCESS_LD,
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1_DCACHE_REFILL_LD,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1_DCACHE_ACCESS_ST,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1_DCACHE_MISS_ST,
|
||||
[C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1_DCACHE_PREF_ACCESS,
|
||||
[C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1_DCACHE_PREF_MISS,
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
|
||||
[C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
|
||||
[C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
|
||||
|
||||
[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS,
|
||||
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL,
|
||||
[C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1_ICACHE_PREF_ACCESS,
|
||||
[C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1_ICACHE_PREF_MISS,
|
||||
[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
|
||||
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
|
||||
[C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
|
||||
[C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
|
||||
|
||||
[C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_DTLB_ACCESS_LD,
|
||||
[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_DTLB_REFILL_LD,
|
||||
[C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_DTLB_ACCESS_ST,
|
||||
[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_DTLB_REFILL_ST,
|
||||
[C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
|
||||
[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
|
||||
[C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
|
||||
[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
|
||||
|
||||
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_ITLB_REFILL,
|
||||
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
|
||||
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
|
||||
};
|
||||
|
||||
static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
||||
[PERF_COUNT_HW_CACHE_OP_MAX]
|
||||
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
|
||||
PERF_CACHE_MAP_ALL_UNSUPPORTED,
|
||||
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
|
||||
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
|
||||
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
|
||||
|
||||
[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
|
||||
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
|
||||
|
||||
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
|
||||
[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
|
||||
|
||||
[C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
|
||||
[C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
|
||||
[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
|
||||
[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
|
||||
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
|
||||
[C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
|
||||
[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
|
||||
|
||||
[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
|
||||
[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
|
||||
};
|
||||
|
||||
static ssize_t
|
||||
armv8pmu_events_sysfs_show(struct device *dev,
|
||||
struct device_attribute *attr, char *page)
|
||||
{
|
||||
struct perf_pmu_events_attr *pmu_attr;
|
||||
|
||||
pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
|
||||
|
||||
return sprintf(page, "event=0x%03llx\n", pmu_attr->id);
|
||||
}
|
||||
|
||||
#define ARMV8_EVENT_ATTR_RESOLVE(m) #m
|
||||
#define ARMV8_EVENT_ATTR(name, config) \
|
||||
PMU_EVENT_ATTR_STRING(name, armv8_event_attr_##name, \
|
||||
"event=" ARMV8_EVENT_ATTR_RESOLVE(config))
|
||||
PMU_EVENT_ATTR(name, armv8_event_attr_##name, \
|
||||
config, armv8pmu_events_sysfs_show)
|
||||
|
||||
ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR);
|
||||
ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL);
|
||||
ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_ITLB_REFILL);
|
||||
ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL);
|
||||
ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS);
|
||||
ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_DTLB_REFILL);
|
||||
ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_MEM_READ);
|
||||
ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_MEM_WRITE);
|
||||
ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED);
|
||||
ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR);
|
||||
ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL);
|
||||
ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL);
|
||||
ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL);
|
||||
ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE);
|
||||
ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL);
|
||||
ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED);
|
||||
ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED);
|
||||
ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED);
|
||||
ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN);
|
||||
ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_EXECUTED);
|
||||
ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE);
|
||||
ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE);
|
||||
ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH);
|
||||
ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN);
|
||||
ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS);
|
||||
ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED);
|
||||
ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES);
|
||||
ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED);
|
||||
ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN);
|
||||
ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED);
|
||||
ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED);
|
||||
ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED);
|
||||
ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED);
|
||||
ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED);
|
||||
ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED);
|
||||
ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES);
|
||||
ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED);
|
||||
ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS);
|
||||
ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS);
|
||||
ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB);
|
||||
ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS);
|
||||
ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL);
|
||||
ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2_CACHE_WB);
|
||||
ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE);
|
||||
ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB);
|
||||
ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE);
|
||||
ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL);
|
||||
ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB);
|
||||
ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS);
|
||||
ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEM_ERROR);
|
||||
ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC);
|
||||
ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE);
|
||||
ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR);
|
||||
ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC);
|
||||
ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED);
|
||||
ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES);
|
||||
ARMV8_EVENT_ATTR(chain, ARMV8_PMUV3_PERFCTR_CHAIN);
|
||||
/* Don't expose the chain event in /sys, since it's useless in isolation */
|
||||
ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE);
|
||||
ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE);
|
||||
ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED);
|
||||
|
|
@ -297,9 +432,9 @@ ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL);
|
|||
ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE);
|
||||
ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB);
|
||||
ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL);
|
||||
ARMV8_EVENT_ATTR(l21_tlb_refill, ARMV8_PMUV3_PERFCTR_L21_TLB_REFILL);
|
||||
ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL);
|
||||
ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB);
|
||||
ARMV8_EVENT_ATTR(l21_tlb, ARMV8_PMUV3_PERFCTR_L21_TLB);
|
||||
ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB);
|
||||
|
||||
static struct attribute *armv8_pmuv3_event_attrs[] = {
|
||||
&armv8_event_attr_sw_incr.attr.attr,
|
||||
|
|
@ -332,7 +467,6 @@ static struct attribute *armv8_pmuv3_event_attrs[] = {
|
|||
&armv8_event_attr_inst_spec.attr.attr,
|
||||
&armv8_event_attr_ttbr_write_retired.attr.attr,
|
||||
&armv8_event_attr_bus_cycles.attr.attr,
|
||||
&armv8_event_attr_chain.attr.attr,
|
||||
&armv8_event_attr_l1d_cache_allocate.attr.attr,
|
||||
&armv8_event_attr_l2d_cache_allocate.attr.attr,
|
||||
&armv8_event_attr_br_retired.attr.attr,
|
||||
|
|
@ -348,15 +482,33 @@ static struct attribute *armv8_pmuv3_event_attrs[] = {
|
|||
&armv8_event_attr_l3d_cache.attr.attr,
|
||||
&armv8_event_attr_l3d_cache_wb.attr.attr,
|
||||
&armv8_event_attr_l2d_tlb_refill.attr.attr,
|
||||
&armv8_event_attr_l21_tlb_refill.attr.attr,
|
||||
&armv8_event_attr_l2i_tlb_refill.attr.attr,
|
||||
&armv8_event_attr_l2d_tlb.attr.attr,
|
||||
&armv8_event_attr_l21_tlb.attr.attr,
|
||||
&armv8_event_attr_l2i_tlb.attr.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static umode_t
|
||||
armv8pmu_event_attr_is_visible(struct kobject *kobj,
|
||||
struct attribute *attr, int unused)
|
||||
{
|
||||
struct device *dev = kobj_to_dev(kobj);
|
||||
struct pmu *pmu = dev_get_drvdata(dev);
|
||||
struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
|
||||
struct perf_pmu_events_attr *pmu_attr;
|
||||
|
||||
pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
|
||||
|
||||
if (test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
|
||||
return attr->mode;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct attribute_group armv8_pmuv3_events_attr_group = {
|
||||
.name = "events",
|
||||
.attrs = armv8_pmuv3_event_attrs,
|
||||
.is_visible = armv8pmu_event_attr_is_visible,
|
||||
};
|
||||
|
||||
PMU_FORMAT_ATTR(event, "config:0-9");
|
||||
|
|
@ -397,16 +549,14 @@ static const struct attribute_group *armv8_pmuv3_attr_groups[] = {
|
|||
|
||||
static inline u32 armv8pmu_pmcr_read(void)
|
||||
{
|
||||
u32 val;
|
||||
asm volatile("mrs %0, pmcr_el0" : "=r" (val));
|
||||
return val;
|
||||
return read_sysreg(pmcr_el0);
|
||||
}
|
||||
|
||||
static inline void armv8pmu_pmcr_write(u32 val)
|
||||
{
|
||||
val &= ARMV8_PMU_PMCR_MASK;
|
||||
isb();
|
||||
asm volatile("msr pmcr_el0, %0" :: "r" (val));
|
||||
write_sysreg(val, pmcr_el0);
|
||||
}
|
||||
|
||||
static inline int armv8pmu_has_overflowed(u32 pmovsr)
|
||||
|
|
@ -428,7 +578,7 @@ static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
|
|||
static inline int armv8pmu_select_counter(int idx)
|
||||
{
|
||||
u32 counter = ARMV8_IDX_TO_COUNTER(idx);
|
||||
asm volatile("msr pmselr_el0, %0" :: "r" (counter));
|
||||
write_sysreg(counter, pmselr_el0);
|
||||
isb();
|
||||
|
||||
return idx;
|
||||
|
|
@ -445,9 +595,9 @@ static inline u32 armv8pmu_read_counter(struct perf_event *event)
|
|||
pr_err("CPU%u reading wrong counter %d\n",
|
||||
smp_processor_id(), idx);
|
||||
else if (idx == ARMV8_IDX_CYCLE_COUNTER)
|
||||
asm volatile("mrs %0, pmccntr_el0" : "=r" (value));
|
||||
value = read_sysreg(pmccntr_el0);
|
||||
else if (armv8pmu_select_counter(idx) == idx)
|
||||
asm volatile("mrs %0, pmxevcntr_el0" : "=r" (value));
|
||||
value = read_sysreg(pmxevcntr_el0);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
|
@ -469,47 +619,47 @@ static inline void armv8pmu_write_counter(struct perf_event *event, u32 value)
|
|||
*/
|
||||
u64 value64 = 0xffffffff00000000ULL | value;
|
||||
|
||||
asm volatile("msr pmccntr_el0, %0" :: "r" (value64));
|
||||
write_sysreg(value64, pmccntr_el0);
|
||||
} else if (armv8pmu_select_counter(idx) == idx)
|
||||
asm volatile("msr pmxevcntr_el0, %0" :: "r" (value));
|
||||
write_sysreg(value, pmxevcntr_el0);
|
||||
}
|
||||
|
||||
static inline void armv8pmu_write_evtype(int idx, u32 val)
|
||||
{
|
||||
if (armv8pmu_select_counter(idx) == idx) {
|
||||
val &= ARMV8_PMU_EVTYPE_MASK;
|
||||
asm volatile("msr pmxevtyper_el0, %0" :: "r" (val));
|
||||
write_sysreg(val, pmxevtyper_el0);
|
||||
}
|
||||
}
|
||||
|
||||
static inline int armv8pmu_enable_counter(int idx)
|
||||
{
|
||||
u32 counter = ARMV8_IDX_TO_COUNTER(idx);
|
||||
asm volatile("msr pmcntenset_el0, %0" :: "r" (BIT(counter)));
|
||||
write_sysreg(BIT(counter), pmcntenset_el0);
|
||||
return idx;
|
||||
}
|
||||
|
||||
static inline int armv8pmu_disable_counter(int idx)
|
||||
{
|
||||
u32 counter = ARMV8_IDX_TO_COUNTER(idx);
|
||||
asm volatile("msr pmcntenclr_el0, %0" :: "r" (BIT(counter)));
|
||||
write_sysreg(BIT(counter), pmcntenclr_el0);
|
||||
return idx;
|
||||
}
|
||||
|
||||
static inline int armv8pmu_enable_intens(int idx)
|
||||
{
|
||||
u32 counter = ARMV8_IDX_TO_COUNTER(idx);
|
||||
asm volatile("msr pmintenset_el1, %0" :: "r" (BIT(counter)));
|
||||
write_sysreg(BIT(counter), pmintenset_el1);
|
||||
return idx;
|
||||
}
|
||||
|
||||
static inline int armv8pmu_disable_intens(int idx)
|
||||
{
|
||||
u32 counter = ARMV8_IDX_TO_COUNTER(idx);
|
||||
asm volatile("msr pmintenclr_el1, %0" :: "r" (BIT(counter)));
|
||||
write_sysreg(BIT(counter), pmintenclr_el1);
|
||||
isb();
|
||||
/* Clear the overflow flag in case an interrupt is pending. */
|
||||
asm volatile("msr pmovsclr_el0, %0" :: "r" (BIT(counter)));
|
||||
write_sysreg(BIT(counter), pmovsclr_el0);
|
||||
isb();
|
||||
|
||||
return idx;
|
||||
|
|
@ -520,11 +670,11 @@ static inline u32 armv8pmu_getreset_flags(void)
|
|||
u32 value;
|
||||
|
||||
/* Read */
|
||||
asm volatile("mrs %0, pmovsclr_el0" : "=r" (value));
|
||||
value = read_sysreg(pmovsclr_el0);
|
||||
|
||||
/* Write to clear flags */
|
||||
value &= ARMV8_PMU_OVSR_MASK;
|
||||
asm volatile("msr pmovsclr_el0, %0" :: "r" (value));
|
||||
write_sysreg(value, pmovsclr_el0);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
|
@ -685,7 +835,7 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
|
|||
unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
|
||||
|
||||
/* Always place a cycle counter into the cycle counter. */
|
||||
if (evtype == ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES) {
|
||||
if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
|
||||
if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
|
||||
return -EAGAIN;
|
||||
|
||||
|
|
@ -781,22 +931,38 @@ static int armv8_thunder_map_event(struct perf_event *event)
|
|||
ARMV8_PMU_EVTYPE_EVENT);
|
||||
}
|
||||
|
||||
static void armv8pmu_read_num_pmnc_events(void *info)
|
||||
static int armv8_vulcan_map_event(struct perf_event *event)
|
||||
{
|
||||
int *nb_cnt = info;
|
||||
|
||||
/* Read the nb of CNTx counters supported from PMNC */
|
||||
*nb_cnt = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
|
||||
|
||||
/* Add the CPU cycles counter */
|
||||
*nb_cnt += 1;
|
||||
return armpmu_map_event(event, &armv8_vulcan_perf_map,
|
||||
&armv8_vulcan_perf_cache_map,
|
||||
ARMV8_PMU_EVTYPE_EVENT);
|
||||
}
|
||||
|
||||
static int armv8pmu_probe_num_events(struct arm_pmu *arm_pmu)
|
||||
static void __armv8pmu_probe_pmu(void *info)
|
||||
{
|
||||
return smp_call_function_any(&arm_pmu->supported_cpus,
|
||||
armv8pmu_read_num_pmnc_events,
|
||||
&arm_pmu->num_events, 1);
|
||||
struct arm_pmu *cpu_pmu = info;
|
||||
u32 pmceid[2];
|
||||
|
||||
/* Read the nb of CNTx counters supported from PMNC */
|
||||
cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
|
||||
& ARMV8_PMU_PMCR_N_MASK;
|
||||
|
||||
/* Add the CPU cycles counter */
|
||||
cpu_pmu->num_events += 1;
|
||||
|
||||
pmceid[0] = read_sysreg(pmceid0_el0);
|
||||
pmceid[1] = read_sysreg(pmceid1_el0);
|
||||
|
||||
bitmap_from_u32array(cpu_pmu->pmceid_bitmap,
|
||||
ARMV8_PMUV3_MAX_COMMON_EVENTS, pmceid,
|
||||
ARRAY_SIZE(pmceid));
|
||||
}
|
||||
|
||||
static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return smp_call_function_any(&cpu_pmu->supported_cpus,
|
||||
__armv8pmu_probe_pmu,
|
||||
cpu_pmu, 1);
|
||||
}
|
||||
|
||||
static void armv8_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
|
|
@ -819,7 +985,8 @@ static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
|
|||
armv8_pmu_init(cpu_pmu);
|
||||
cpu_pmu->name = "armv8_pmuv3";
|
||||
cpu_pmu->map_event = armv8_pmuv3_map_event;
|
||||
return armv8pmu_probe_num_events(cpu_pmu);
|
||||
cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups;
|
||||
return armv8pmu_probe_pmu(cpu_pmu);
|
||||
}
|
||||
|
||||
static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
|
|
@ -828,7 +995,7 @@ static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
|
|||
cpu_pmu->name = "armv8_cortex_a53";
|
||||
cpu_pmu->map_event = armv8_a53_map_event;
|
||||
cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups;
|
||||
return armv8pmu_probe_num_events(cpu_pmu);
|
||||
return armv8pmu_probe_pmu(cpu_pmu);
|
||||
}
|
||||
|
||||
static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
|
|
@ -837,7 +1004,7 @@ static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
|
|||
cpu_pmu->name = "armv8_cortex_a57";
|
||||
cpu_pmu->map_event = armv8_a57_map_event;
|
||||
cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups;
|
||||
return armv8pmu_probe_num_events(cpu_pmu);
|
||||
return armv8pmu_probe_pmu(cpu_pmu);
|
||||
}
|
||||
|
||||
static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
|
|
@ -846,7 +1013,7 @@ static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
|
|||
cpu_pmu->name = "armv8_cortex_a72";
|
||||
cpu_pmu->map_event = armv8_a57_map_event;
|
||||
cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups;
|
||||
return armv8pmu_probe_num_events(cpu_pmu);
|
||||
return armv8pmu_probe_pmu(cpu_pmu);
|
||||
}
|
||||
|
||||
static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
|
|
@ -855,7 +1022,16 @@ static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
|
|||
cpu_pmu->name = "armv8_cavium_thunder";
|
||||
cpu_pmu->map_event = armv8_thunder_map_event;
|
||||
cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups;
|
||||
return armv8pmu_probe_num_events(cpu_pmu);
|
||||
return armv8pmu_probe_pmu(cpu_pmu);
|
||||
}
|
||||
|
||||
static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
armv8_pmu_init(cpu_pmu);
|
||||
cpu_pmu->name = "armv8_brcm_vulcan";
|
||||
cpu_pmu->map_event = armv8_vulcan_map_event;
|
||||
cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups;
|
||||
return armv8pmu_probe_pmu(cpu_pmu);
|
||||
}
|
||||
|
||||
static const struct of_device_id armv8_pmu_of_device_ids[] = {
|
||||
|
|
@ -864,6 +1040,7 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
|
|||
{.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init},
|
||||
{.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init},
|
||||
{.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init},
|
||||
{.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init},
|
||||
{},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -105,6 +105,8 @@ struct arm_pmu {
|
|||
struct mutex reserve_mutex;
|
||||
u64 max_period;
|
||||
bool secure_access; /* 32-bit ARM only */
|
||||
#define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40
|
||||
DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
|
||||
struct platform_device *plat_device;
|
||||
struct pmu_hw_events __percpu *hw_events;
|
||||
struct notifier_block hotplug_nb;
|
||||
|
|
|
|||
Loading…
Reference in New Issue