V4L/DVB: Complete rewrite of the DiB3000mc-driver
A complete rewrite of the DiB3000MC/P driver has been done. It is now much more easy to maintain and to get improvements inside. Additionally the tuning time has been reduced and the usage of the driver is much more understandable now. Signed-off-by: Patrick Boettcher <pboettcher@dibcom.fr> Signed-off-by: Francois KANOUNNIKOFF <fkanounnikoff@dibcom.fr> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
This commit is contained in:
Patrick Boettcher
Mauro Carvalho Chehab
parent
74340b0a8b
commit
b7571f8d7e
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@ -131,9 +131,6 @@ static int dibusb_i2c_xfer(struct i2c_adapter *adap,struct i2c_msg msg[],int num
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if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
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return -EAGAIN;
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if (num > 2)
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warn("more than 2 i2c messages at a time is not handled yet. TODO.");
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for (i = 0; i < num; i++) {
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/* write/read request */
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if (i+1 < num && (msg[i+1].flags & I2C_M_RD)) {
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@ -168,31 +165,137 @@ int dibusb_read_eeprom_byte(struct dvb_usb_device *d, u8 offs, u8 *val)
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}
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EXPORT_SYMBOL(dibusb_read_eeprom_byte);
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static const struct dib3000p_agc_config dib3000p_agc_panasonic_env57h1xd5 = {
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{ 0x51, 0x301d, 0x0, 0x1cc7, 0xdc29, 0x570a,
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0xbae1, 0x8ccd, 0x3b6d, 0x551d, 0xa, 0x951e }
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/* 3000MC/P stuff */
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// Config Adjacent channels Perf -cal22
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static struct dibx000_agc_config dib3000p_mt2060_agc_config = {
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.band_caps = BAND_VHF | BAND_UHF,
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.setup = (0 << 15) | (0 << 14) | (1 << 13) | (1 << 12) | (29 << 0),
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.agc1_max = 48497,
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.agc1_min = 23593,
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.agc2_max = 46531,
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.agc2_min = 24904,
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.agc1_pt1 = 0x65,
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.agc1_pt2 = 0x69,
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.agc1_slope1 = 0x51,
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.agc1_slope2 = 0x27,
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.agc2_pt1 = 0,
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.agc2_pt2 = 0x33,
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.agc2_slope1 = 0x35,
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.agc2_slope2 = 0x37,
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};
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static const struct dib3000p_agc_config dib3000p_agc_microtune_mt2060 = {
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{ 0x196, 0x301d, 0x0, 0x1cc7, 0xffff, 0x5c29,
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0xa8f6, 0x5eb8, 0x65ff, 0x40ff, 0x8a, 0x1114 }
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static struct dib3000mc_config stk3000p_dib3000p_config = {
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&dib3000p_mt2060_agc_config,
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.max_time = 0x196,
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.ln_adc_level = 0x1cc7,
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.output_mpeg2_in_188_bytes = 1,
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};
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static struct mt2060_config stk3000p_mt2060_config = {
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.i2c_address = 0x60,
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static struct dibx000_agc_config dib3000p_panasonic_agc_config = {
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.setup = (0 << 15) | (0 << 14) | (1 << 13) | (1 << 12) | (29 << 0),
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.agc1_max = 56361,
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.agc1_min = 22282,
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.agc2_max = 43254,
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.agc2_min = 36045,
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.agc1_pt1 = 0x65,
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.agc1_pt2 = 0xff,
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.agc1_slope1 = 0x40,
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.agc1_slope2 = 0xff,
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.agc2_pt1 = 0,
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.agc2_pt2 = 0x8a,
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.agc2_slope1 = 0x11,
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.agc2_slope2 = 0x14,
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};
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static struct dib3000mc_config mod3000p_dib3000p_config = {
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&dib3000p_panasonic_agc_config,
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.max_time = 0x51,
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.ln_adc_level = 0x1cc7,
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.output_mpeg2_in_188_bytes = 1,
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};
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int dibusb_dib3000mc_frontend_attach(struct dvb_usb_device *d)
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{
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struct dib3000_config demod_cfg;
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struct dibusb_state *st = d->priv;
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if (dib3000mc_attach(&d->i2c_adap, 1, DEFAULT_DIB3000P_I2C_ADDRESS, 0, &mod3000p_dib3000p_config, &d->fe) == 0) {
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if (d->priv != NULL) {
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struct dibusb_state *st = d->priv;
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st->ops.pid_parse = dib3000mc_pid_parse;
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st->ops.pid_ctrl = dib3000mc_pid_control;
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}
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return 0;
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}
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return -ENODEV;
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}
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EXPORT_SYMBOL(dibusb_dib3000mc_frontend_attach);
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static struct mt2060_config stk3000p_mt2060_config = {
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0x60
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};
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int dibusb_dib3000mc_tuner_attach (struct dvb_usb_device *d)
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{
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return -ENODEV;
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struct dibusb_state *st = d->priv;
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int ret;
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u8 a,b;
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u16 if1 = 1220;
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struct i2c_adapter *tun_i2c;
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// First IF calibration for Liteon Sticks
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if (d->udev->descriptor.idVendor == USB_VID_LITEON &&
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d->udev->descriptor.idProduct == USB_PID_LITEON_DVB_T_WARM) {
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dibusb_read_eeprom_byte(d,0x7E,&a);
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dibusb_read_eeprom_byte(d,0x7F,&b);
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if (a == 0x00)
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if1 += b;
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else if (a == 0x80)
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if1 -= b;
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else
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warn("LITE-ON DVB-T: Strange IF1 calibration :%2X %2X\n", a, b);
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} else if (d->udev->descriptor.idVendor == USB_VID_DIBCOM &&
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d->udev->descriptor.idProduct == USB_PID_DIBCOM_MOD3001_WARM) {
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u8 desc;
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dibusb_read_eeprom_byte(d, 7, &desc);
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if (desc == 2) {
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a = 127;
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do {
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dibusb_read_eeprom_byte(d, a, &desc);
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a--;
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} while (a > 7 && (desc == 0xff || desc == 0x00));
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if (desc & 0x80)
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if1 -= (0xff - desc);
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else
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if1 += desc;
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}
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}
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tun_i2c = dib3000mc_get_tuner_i2c_master(d->fe, 1);
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if ((ret = mt2060_attach(d->fe, tun_i2c, &stk3000p_mt2060_config, if1)) != 0) {
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/* not found - use panasonic pll parameters */
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if (dvb_pll_attach(d->fe, 0x60, tun_i2c, &dvb_pll_env57h1xd5) == NULL)
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return -ENOMEM;
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} else {
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st->mt2060_present = 1;
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/* set the correct parameters for the dib3000p */
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dib3000mc_set_config(d->fe, &stk3000p_dib3000p_config);
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}
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return 0;
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}
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EXPORT_SYMBOL(dibusb_dib3000mc_tuner_attach);
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@ -20,11 +20,12 @@ static int dibusb_dib3000mb_frontend_attach(struct dvb_usb_device *d)
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struct dibusb_state *st = d->priv;
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demod_cfg.demod_address = 0x8;
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demod_cfg.pll_set = dvb_usb_pll_set_i2c;
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demod_cfg.pll_init = dvb_usb_pll_init_i2c;
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if ((d->fe = dib3000mb_attach(&demod_cfg,&d->i2c_adap,&st->ops)) == NULL)
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if ((d->fe = dib3000mb_attach(&demod_cfg,&d->i2c_adap,&st->ops)) == NULL) {
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d->fe->ops.tuner_ops.init = dvb_usb_tuner_init_i2c;
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d->fe->ops.tuner_ops.set_params = dvb_usb_tuner_set_params_i2c;
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return -ENODEV;
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}
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d->tuner_pass_ctrl = st->ops.tuner_pass_ctrl;
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@ -17,6 +17,7 @@
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#include "dvb-usb.h"
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#include "dib3000.h"
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#include "dib3000mc.h"
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#include "mt2060.h"
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/*
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@ -179,16 +179,15 @@ int dvb_usb_fe_init(struct dvb_usb_device* d)
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return 0;
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}
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d->props.frontend_attach(d);
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/* re-assign sleep and wakeup functions */
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if (d->fe != NULL) {
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if (d->props.frontend_attach(d) == 0 && d->fe != NULL) {
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d->fe_init = d->fe->ops.init; d->fe->ops.init = dvb_usb_fe_wakeup;
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d->fe_sleep = d->fe->ops.sleep; d->fe->ops.sleep = dvb_usb_fe_sleep;
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if (dvb_register_frontend(&d->dvb_adap, d->fe)) {
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err("Frontend registration failed.");
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dvb_frontend_detach(d->fe);
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if (d->fe->ops.release)
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d->fe->ops.release(d->fe);
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d->fe = NULL;
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return -ENODEV;
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}
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@ -203,9 +202,7 @@ int dvb_usb_fe_init(struct dvb_usb_device* d)
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int dvb_usb_fe_exit(struct dvb_usb_device *d)
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{
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if (d->fe != NULL) {
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if (d->fe != NULL)
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dvb_unregister_frontend(d->fe);
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dvb_frontend_detach(d->fe);
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}
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return 0;
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}
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@ -12,7 +12,7 @@ obj-$(CONFIG_DVB_CX24110) += cx24110.o
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obj-$(CONFIG_DVB_TDA8083) += tda8083.o
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obj-$(CONFIG_DVB_L64781) += l64781.o
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obj-$(CONFIG_DVB_DIB3000MB) += dib3000mb.o
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obj-$(CONFIG_DVB_DIB3000MC) += dib3000mc.o
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obj-$(CONFIG_DVB_DIB3000MC) += dib3000mc.o dibx000_common.o
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obj-$(CONFIG_DVB_MT312) += mt312.o
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obj-$(CONFIG_DVB_VES1820) += ves1820.o
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obj-$(CONFIG_DVB_VES1X93) += ves1x93.o
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@ -31,6 +31,8 @@ obj-$(CONFIG_DVB_BCM3510) += bcm3510.o
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obj-$(CONFIG_DVB_S5H1420) += s5h1420.o
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obj-$(CONFIG_DVB_LGDT330X) += lgdt330x.o
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obj-$(CONFIG_DVB_CX24123) += cx24123.o
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obj-$(CONFIG_DVB_LNBP21) += lnbp21.o
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obj-$(CONFIG_DVB_ISL6421) += isl6421.o
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obj-$(CONFIG_DVB_TDA10086) += tda10086.o
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obj-$(CONFIG_DVB_TDA826X) += tda826x.o
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obj-$(CONFIG_DVB_TUNER_MT2060) += mt2060.o
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@ -26,20 +26,10 @@
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#include <linux/dvb/frontend.h>
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struct dib3000p_agc_config {
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u16 val[12];
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};
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struct dib3000_config
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{
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/* the demodulator's i2c address */
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u8 demod_address;
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const struct dib3000p_agc_config *agc;
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/* PLL maintenance and the i2c address of the PLL */
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int (*pll_init)(struct dvb_frontend *fe);
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int (*pll_set)(struct dvb_frontend *fe, struct dvb_frontend_parameters* params);
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};
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struct dib_fe_xfer_ops
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@ -51,11 +41,16 @@ struct dib_fe_xfer_ops
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int (*tuner_pass_ctrl)(struct dvb_frontend *fe, int onoff, u8 pll_ctrl);
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};
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#if defined(CONFIG_DVB_DIB3000MB) || defined(CONFIG_DVB_DIB3000MB_MODULE)
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extern struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
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struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops);
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#else
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static inline struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
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struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
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{
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printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __FUNCTION__);
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return NULL;
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}
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#endif // CONFIG_DVB_DIB3000MB
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extern struct dvb_frontend* dib3000mc_attach(const struct dib3000_config* config,
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struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops);
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extern int dib3000mc_set_agc_config(struct dvb_frontend *fe, const struct dib3000p_agc_config *agc);
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#endif // DIB3000_H
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@ -83,9 +83,6 @@
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#define DIB3000_TUNER_WRITE_ENABLE(a) (0xffff & (a << 8))
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#define DIB3000_TUNER_WRITE_DISABLE(a) (0xffff & ((a << 8) | (1 << 7)))
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/* for auto search */
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extern u16 dib3000_seq[2][2][2];
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#define DIB3000_REG_MANUFACTOR_ID ( 1025)
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#define DIB3000_I2C_ID_DIBCOM (0x01b3)
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File diff suppressed because it is too large
Load Diff
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@ -1,404 +0,0 @@
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/*
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* dib3000mc_priv.h
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*
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* Copyright (C) 2004 Patrick Boettcher (patrick.boettcher@desy.de)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation, version 2.
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*
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* for more information see dib3000mc.c .
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*/
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#ifndef __DIB3000MC_PRIV_H__
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#define __DIB3000MC_PRIV_H__
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/*
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* Demodulator parameters
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* reg: 0 1 1 1 11 11 111
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* | | | | | |
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* | | | | | +-- alpha (000=0, 001=1, 010=2, 100=4)
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* | | | | +----- constellation (00=QPSK, 01=16QAM, 10=64QAM)
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* | | | +-------- guard (00=1/32, 01=1/16, 10=1/8, 11=1/4)
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* | | +----------- transmission mode (0=2k, 1=8k)
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* | |
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* | +-------------- restart autosearch for parameters
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* +---------------- restart the demodulator
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* reg: 181 1 111 1
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* | | |
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* | | +- FEC applies for HP or LP (0=LP, 1=HP)
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* | +---- FEC rate (001=1/2, 010=2/3, 011=3/4, 101=5/6, 111=7/8)
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* +------- hierarchy on (0=no, 1=yes)
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*/
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/* demodulator tuning parameter and restart options */
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#define DIB3000MC_REG_DEMOD_PARM ( 0)
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#define DIB3000MC_DEMOD_PARM(a,c,g,t) ( \
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(0x7 & a) | \
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((0x3 & c) << 3) | \
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((0x3 & g) << 5) | \
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((0x1 & t) << 7) )
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#define DIB3000MC_DEMOD_RST_AUTO_SRCH_ON (1 << 8)
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#define DIB3000MC_DEMOD_RST_AUTO_SRCH_OFF (0 << 8)
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#define DIB3000MC_DEMOD_RST_DEMOD_ON (1 << 9)
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#define DIB3000MC_DEMOD_RST_DEMOD_OFF (0 << 9)
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/* register for hierarchy parameters */
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#define DIB3000MC_REG_HRCH_PARM ( 181)
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#define DIB3000MC_HRCH_PARM(s,f,h) ( \
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(0x1 & s) | \
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((0x7 & f) << 1) | \
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((0x1 & h) << 4) )
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/* timeout ??? */
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#define DIB3000MC_REG_UNK_1 ( 1)
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#define DIB3000MC_UNK_1 ( 0x04)
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/* timeout ??? */
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#define DIB3000MC_REG_UNK_2 ( 2)
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#define DIB3000MC_UNK_2 ( 0x04)
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/* timeout ??? */
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#define DIB3000MC_REG_UNK_3 ( 3)
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#define DIB3000MC_UNK_3 (0x1000)
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#define DIB3000MC_REG_UNK_4 ( 4)
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#define DIB3000MC_UNK_4 (0x0814)
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/* timeout ??? */
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#define DIB3000MC_REG_SEQ_TPS ( 5)
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#define DIB3000MC_SEQ_TPS_DEFAULT ( 1)
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#define DIB3000MC_SEQ_TPS(s,t) ( \
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((s & 0x0f) << 4) | \
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((t & 0x01) << 8) )
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#define DIB3000MC_IS_TPS(v) ((v << 8) & 0x1)
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#define DIB3000MC_IS_AS(v) ((v >> 4) & 0xf)
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/* parameters for the bandwidth */
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#define DIB3000MC_REG_BW_TIMOUT_MSB ( 6)
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#define DIB3000MC_REG_BW_TIMOUT_LSB ( 7)
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static u16 dib3000mc_reg_bandwidth[] = { 6,7,8,9,10,11,16,17 };
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/*static u16 dib3000mc_bandwidth_5mhz[] =
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{ 0x28, 0x9380, 0x87, 0x4100, 0x2a4, 0x4500, 0x1, 0xb0d0 };*/
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static u16 dib3000mc_bandwidth_6mhz[] =
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{ 0x21, 0xd040, 0x70, 0xb62b, 0x233, 0x8ed5, 0x1, 0xb0d0 };
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static u16 dib3000mc_bandwidth_7mhz[] =
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{ 0x1c, 0xfba5, 0x60, 0x9c25, 0x1e3, 0x0cb7, 0x1, 0xb0d0 };
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static u16 dib3000mc_bandwidth_8mhz[] =
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||||
{ 0x19, 0x5c30, 0x54, 0x88a0, 0x1a6, 0xab20, 0x1, 0xb0d0 };
|
||||
|
||||
static u16 dib3000mc_reg_bandwidth_general[] = { 12,13,14,15 };
|
||||
static u16 dib3000mc_bandwidth_general[] = { 0x0000, 0x03e8, 0x0000, 0x03f2 };
|
||||
|
||||
/* lock mask */
|
||||
#define DIB3000MC_REG_LOCK_MASK ( 15)
|
||||
#define DIB3000MC_ACTIVATE_LOCK_MASK (0x0800)
|
||||
|
||||
/* reset the uncorrected packet count (??? do it 5 times) */
|
||||
#define DIB3000MC_REG_RST_UNC ( 18)
|
||||
#define DIB3000MC_RST_UNC_ON ( 1)
|
||||
#define DIB3000MC_RST_UNC_OFF ( 0)
|
||||
|
||||
#define DIB3000MC_REG_UNK_19 ( 19)
|
||||
#define DIB3000MC_UNK_19 ( 0)
|
||||
|
||||
/* DDS frequency value (IF position) and inversion bit */
|
||||
#define DIB3000MC_REG_INVERSION ( 21)
|
||||
#define DIB3000MC_REG_SET_DDS_FREQ_MSB ( 21)
|
||||
#define DIB3000MC_DDS_FREQ_MSB_INV_OFF (0x0164)
|
||||
#define DIB3000MC_DDS_FREQ_MSB_INV_ON (0x0364)
|
||||
|
||||
#define DIB3000MC_REG_SET_DDS_FREQ_LSB ( 22)
|
||||
#define DIB3000MC_DDS_FREQ_LSB (0x463d)
|
||||
|
||||
/* timing frequencies setting */
|
||||
#define DIB3000MC_REG_TIMING_FREQ_MSB ( 23)
|
||||
#define DIB3000MC_REG_TIMING_FREQ_LSB ( 24)
|
||||
#define DIB3000MC_CLOCK_REF (0x151fd1)
|
||||
|
||||
//static u16 dib3000mc_reg_timing_freq[] = { 23,24 };
|
||||
|
||||
//static u16 dib3000mc_timing_freq[][2] = {
|
||||
// { 0x69, 0x9f18 }, /* 5 MHz */
|
||||
// { 0x7e ,0xbee9 }, /* 6 MHz */
|
||||
// { 0x93 ,0xdebb }, /* 7 MHz */
|
||||
// { 0xa8 ,0xfe8c }, /* 8 MHz */
|
||||
//};
|
||||
|
||||
/* timeout ??? */
|
||||
static u16 dib3000mc_reg_offset[] = { 26,33 };
|
||||
|
||||
static u16 dib3000mc_offset[][2] = {
|
||||
{ 26240, 5 }, /* default */
|
||||
{ 30336, 6 }, /* 8K */
|
||||
{ 38528, 8 }, /* 2K */
|
||||
};
|
||||
|
||||
#define DIB3000MC_REG_ISI ( 29)
|
||||
#define DIB3000MC_ISI_DEFAULT (0x1073)
|
||||
#define DIB3000MC_ISI_ACTIVATE (0x0000)
|
||||
#define DIB3000MC_ISI_INHIBIT (0x0200)
|
||||
|
||||
/* impulse noise control */
|
||||
static u16 dib3000mc_reg_imp_noise_ctl[] = { 34,35 };
|
||||
|
||||
static u16 dib3000mc_imp_noise_ctl[][2] = {
|
||||
{ 0x1294, 0x1ff8 }, /* mode 0 */
|
||||
{ 0x1294, 0x1ff8 }, /* mode 1 */
|
||||
{ 0x1294, 0x1ff8 }, /* mode 2 */
|
||||
{ 0x1294, 0x1ff8 }, /* mode 3 */
|
||||
{ 0x1294, 0x1ff8 }, /* mode 4 */
|
||||
};
|
||||
|
||||
/* AGC loop bandwidth */
|
||||
static u16 dib3000mc_reg_agc_bandwidth[] = { 40,41 };
|
||||
static u16 dib3000mc_agc_bandwidth[] = { 0x119,0x330 };
|
||||
|
||||
static u16 dib3000mc_reg_agc_bandwidth_general[] = { 50,51,52,53,54 };
|
||||
static u16 dib3000mc_agc_bandwidth_general[] =
|
||||
{ 0x8000, 0x91ca, 0x01ba, 0x0087, 0x0087 };
|
||||
|
||||
#define DIB3000MC_REG_IMP_NOISE_55 ( 55)
|
||||
#define DIB3000MC_IMP_NEW_ALGO(w) (w | (1<<10))
|
||||
|
||||
/* Impulse noise params */
|
||||
static u16 dib3000mc_reg_impulse_noise[] = { 55,56,57 };
|
||||
static u16 dib3000mc_impluse_noise[][3] = {
|
||||
{ 0x489, 0x89, 0x72 }, /* 5 MHz */
|
||||
{ 0x4a5, 0xa5, 0x89 }, /* 6 MHz */
|
||||
{ 0x4c0, 0xc0, 0xa0 }, /* 7 MHz */
|
||||
{ 0x4db, 0xdb, 0xb7 }, /* 8 Mhz */
|
||||
};
|
||||
|
||||
static u16 dib3000mc_reg_fft[] = {
|
||||
58,59,60,61,62,63,64,65,66,67,68,69,
|
||||
70,71,72,73,74,75,76,77,78,79,80,81,
|
||||
82,83,84,85,86
|
||||
};
|
||||
|
||||
static u16 dib3000mc_fft_modes[][29] = {
|
||||
{ 0x38, 0x6d9, 0x3f28, 0x7a7, 0x3a74, 0x196, 0x32a, 0x48c,
|
||||
0x3ffe, 0x7f3, 0x2d94, 0x76, 0x53d,
|
||||
0x3ff8, 0x7e3, 0x3320, 0x76, 0x5b3,
|
||||
0x3feb, 0x7d2, 0x365e, 0x76, 0x48c,
|
||||
0x3ffe, 0x5b3, 0x3feb, 0x76, 0x0, 0xd
|
||||
}, /* fft mode 0 */
|
||||
{ 0x3b, 0x6d9, 0x3f28, 0x7a7, 0x3a74, 0x196, 0x32a, 0x48c,
|
||||
0x3ffe, 0x7f3, 0x2d94, 0x76, 0x53d,
|
||||
0x3ff8, 0x7e3, 0x3320, 0x76, 0x5b3,
|
||||
0x3feb, 0x7d2, 0x365e, 0x76, 0x48c,
|
||||
0x3ffe, 0x5b3, 0x3feb, 0x0, 0x8200, 0xd
|
||||
}, /* fft mode 1 */
|
||||
};
|
||||
|
||||
#define DIB3000MC_REG_UNK_88 ( 88)
|
||||
#define DIB3000MC_UNK_88 (0x0410)
|
||||
|
||||
static u16 dib3000mc_reg_bw[] = { 93,94,95,96,97,98 };
|
||||
static u16 dib3000mc_bw[][6] = {
|
||||
{ 0,0,0,0,0,0 }, /* 5 MHz */
|
||||
{ 0,0,0,0,0,0 }, /* 6 MHz */
|
||||
{ 0,0,0,0,0,0 }, /* 7 MHz */
|
||||
{ 0x20, 0x21, 0x20, 0x23, 0x20, 0x27 }, /* 8 MHz */
|
||||
};
|
||||
|
||||
|
||||
/* phase noise control */
|
||||
#define DIB3000MC_REG_UNK_99 ( 99)
|
||||
#define DIB3000MC_UNK_99 (0x0220)
|
||||
|
||||
#define DIB3000MC_REG_SCAN_BOOST ( 100)
|
||||
#define DIB3000MC_SCAN_BOOST_ON ((11 << 6) + 6)
|
||||
#define DIB3000MC_SCAN_BOOST_OFF ((16 << 6) + 9)
|
||||
|
||||
/* timeout ??? */
|
||||
#define DIB3000MC_REG_UNK_110 ( 110)
|
||||
#define DIB3000MC_UNK_110 ( 3277)
|
||||
|
||||
#define DIB3000MC_REG_UNK_111 ( 111)
|
||||
#define DIB3000MC_UNK_111_PH_N_MODE_0 ( 0)
|
||||
#define DIB3000MC_UNK_111_PH_N_MODE_1 (1 << 1)
|
||||
|
||||
/* superious rm config */
|
||||
#define DIB3000MC_REG_UNK_120 ( 120)
|
||||
#define DIB3000MC_UNK_120 ( 8207)
|
||||
|
||||
#define DIB3000MC_REG_UNK_133 ( 133)
|
||||
#define DIB3000MC_UNK_133 ( 15564)
|
||||
|
||||
#define DIB3000MC_REG_UNK_134 ( 134)
|
||||
#define DIB3000MC_UNK_134 ( 0)
|
||||
|
||||
/* adapter config for constellation */
|
||||
static u16 dib3000mc_reg_adp_cfg[] = { 129, 130, 131, 132 };
|
||||
|
||||
static u16 dib3000mc_adp_cfg[][4] = {
|
||||
{ 0x99a, 0x7fae, 0x333, 0x7ff0 }, /* QPSK */
|
||||
{ 0x23d, 0x7fdf, 0x0a4, 0x7ff0 }, /* 16-QAM */
|
||||
{ 0x148, 0x7ff0, 0x0a4, 0x7ff8 }, /* 64-QAM */
|
||||
};
|
||||
|
||||
static u16 dib3000mc_reg_mobile_mode[] = { 139, 140, 141, 175, 1032 };
|
||||
|
||||
static u16 dib3000mc_mobile_mode[][5] = {
|
||||
{ 0x01, 0x0, 0x0, 0x00, 0x12c }, /* fixed */
|
||||
{ 0x01, 0x0, 0x0, 0x00, 0x12c }, /* portable */
|
||||
{ 0x00, 0x0, 0x0, 0x02, 0x000 }, /* mobile */
|
||||
{ 0x00, 0x0, 0x0, 0x02, 0x000 }, /* auto */
|
||||
};
|
||||
|
||||
#define DIB3000MC_REG_DIVERSITY1 ( 177)
|
||||
#define DIB3000MC_DIVERSITY1_DEFAULT ( 1)
|
||||
|
||||
#define DIB3000MC_REG_DIVERSITY2 ( 178)
|
||||
#define DIB3000MC_DIVERSITY2_DEFAULT ( 1)
|
||||
|
||||
#define DIB3000MC_REG_DIVERSITY3 ( 180)
|
||||
#define DIB3000MC_DIVERSITY3_IN_OFF (0xfff0)
|
||||
#define DIB3000MC_DIVERSITY3_IN_ON (0xfff6)
|
||||
|
||||
#define DIB3000MC_REG_FEC_CFG ( 195)
|
||||
#define DIB3000MC_FEC_CFG ( 0x10)
|
||||
|
||||
/*
|
||||
* reg 206, output mode
|
||||
* 1111 1111
|
||||
* |||| ||||
|
||||
* |||| |||+- unk
|
||||
* |||| ||+-- unk
|
||||
* |||| |+--- unk (on by default)
|
||||
* |||| +---- fifo_ctrl (1 = inhibit (flushed), 0 = active (unflushed))
|
||||
* |||+------ pid_parse (1 = enabled, 0 = disabled)
|
||||
* ||+------- outp_188 (1 = TS packet size 188, 0 = packet size 204)
|
||||
* |+-------- unk
|
||||
* +--------- unk
|
||||
*/
|
||||
|
||||
#define DIB3000MC_REG_SMO_MODE ( 206)
|
||||
#define DIB3000MC_SMO_MODE_DEFAULT (1 << 2)
|
||||
#define DIB3000MC_SMO_MODE_FIFO_FLUSH (1 << 3)
|
||||
#define DIB3000MC_SMO_MODE_FIFO_UNFLUSH (0xfff7)
|
||||
#define DIB3000MC_SMO_MODE_PID_PARSE (1 << 4)
|
||||
#define DIB3000MC_SMO_MODE_NO_PID_PARSE (0xffef)
|
||||
#define DIB3000MC_SMO_MODE_188 (1 << 5)
|
||||
#define DIB3000MC_SMO_MODE_SLAVE (DIB3000MC_SMO_MODE_DEFAULT | \
|
||||
DIB3000MC_SMO_MODE_188 | DIB3000MC_SMO_MODE_PID_PARSE | (1<<1))
|
||||
|
||||
#define DIB3000MC_REG_FIFO_THRESHOLD ( 207)
|
||||
#define DIB3000MC_FIFO_THRESHOLD_DEFAULT ( 1792)
|
||||
#define DIB3000MC_FIFO_THRESHOLD_SLAVE ( 512)
|
||||
/*
|
||||
* pidfilter
|
||||
* it is not a hardware pidfilter but a filter which drops all pids
|
||||
* except the ones set. When connected to USB1.1 bandwidth this is important.
|
||||
* DiB3000P/M-C can filter up to 32 PIDs
|
||||
*/
|
||||
#define DIB3000MC_REG_FIRST_PID ( 212)
|
||||
#define DIB3000MC_NUM_PIDS ( 32)
|
||||
|
||||
#define DIB3000MC_REG_OUTMODE ( 244)
|
||||
#define DIB3000MC_OM_PARALLEL_GATED_CLK ( 0)
|
||||
#define DIB3000MC_OM_PAR_CONT_CLK (1 << 11)
|
||||
#define DIB3000MC_OM_SERIAL (2 << 11)
|
||||
#define DIB3000MC_OM_DIVOUT_ON (4 << 11)
|
||||
#define DIB3000MC_OM_SLAVE (DIB3000MC_OM_DIVOUT_ON | DIB3000MC_OM_PAR_CONT_CLK)
|
||||
|
||||
#define DIB3000MC_REG_RF_POWER ( 392)
|
||||
|
||||
#define DIB3000MC_REG_FFT_POSITION ( 407)
|
||||
|
||||
#define DIB3000MC_REG_DDS_FREQ_MSB ( 414)
|
||||
#define DIB3000MC_REG_DDS_FREQ_LSB ( 415)
|
||||
|
||||
#define DIB3000MC_REG_TIMING_OFFS_MSB ( 416)
|
||||
#define DIB3000MC_REG_TIMING_OFFS_LSB ( 417)
|
||||
|
||||
#define DIB3000MC_REG_TUNING_PARM ( 458)
|
||||
#define DIB3000MC_TP_QAM(v) ((v >> 13) & 0x03)
|
||||
#define DIB3000MC_TP_HRCH(v) ((v >> 12) & 0x01)
|
||||
#define DIB3000MC_TP_ALPHA(v) ((v >> 9) & 0x07)
|
||||
#define DIB3000MC_TP_FFT(v) ((v >> 8) & 0x01)
|
||||
#define DIB3000MC_TP_FEC_CR_HP(v) ((v >> 5) & 0x07)
|
||||
#define DIB3000MC_TP_FEC_CR_LP(v) ((v >> 2) & 0x07)
|
||||
#define DIB3000MC_TP_GUARD(v) (v & 0x03)
|
||||
|
||||
#define DIB3000MC_REG_SIGNAL_NOISE_MSB ( 483)
|
||||
#define DIB3000MC_REG_SIGNAL_NOISE_LSB ( 484)
|
||||
|
||||
#define DIB3000MC_REG_MER ( 485)
|
||||
|
||||
#define DIB3000MC_REG_BER_MSB ( 500)
|
||||
#define DIB3000MC_REG_BER_LSB ( 501)
|
||||
|
||||
#define DIB3000MC_REG_PACKET_ERRORS ( 503)
|
||||
|
||||
#define DIB3000MC_REG_PACKET_ERROR_COUNT ( 506)
|
||||
|
||||
#define DIB3000MC_REG_LOCK_507 ( 507)
|
||||
#define DIB3000MC_LOCK_507 (0x0002) // ? name correct ?
|
||||
|
||||
#define DIB3000MC_REG_LOCKING ( 509)
|
||||
#define DIB3000MC_AGC_LOCK(v) (v & 0x8000)
|
||||
#define DIB3000MC_CARRIER_LOCK(v) (v & 0x2000)
|
||||
#define DIB3000MC_MPEG_SYNC_LOCK(v) (v & 0x0080)
|
||||
#define DIB3000MC_MPEG_DATA_LOCK(v) (v & 0x0040)
|
||||
#define DIB3000MC_TPS_LOCK(v) (v & 0x0004)
|
||||
|
||||
#define DIB3000MC_REG_AS_IRQ ( 511)
|
||||
#define DIB3000MC_AS_IRQ_SUCCESS (1 << 1)
|
||||
#define DIB3000MC_AS_IRQ_FAIL ( 1)
|
||||
|
||||
#define DIB3000MC_REG_TUNER ( 769)
|
||||
|
||||
#define DIB3000MC_REG_RST_I2C_ADDR ( 1024)
|
||||
#define DIB3000MC_DEMOD_ADDR_ON ( 1)
|
||||
#define DIB3000MC_DEMOD_ADDR(a) ((a << 4) & 0x03F0)
|
||||
|
||||
#define DIB3000MC_REG_RESTART ( 1027)
|
||||
#define DIB3000MC_RESTART_OFF (0x0000)
|
||||
#define DIB3000MC_RESTART_AGC (0x0800)
|
||||
#define DIB3000MC_RESTART_CONFIG (0x8000)
|
||||
|
||||
#define DIB3000MC_REG_RESTART_VIT ( 1028)
|
||||
#define DIB3000MC_RESTART_VIT_OFF ( 0)
|
||||
#define DIB3000MC_RESTART_VIT_ON ( 1)
|
||||
|
||||
#define DIB3000MC_REG_CLK_CFG_1 ( 1031)
|
||||
#define DIB3000MC_CLK_CFG_1_POWER_UP ( 0)
|
||||
#define DIB3000MC_CLK_CFG_1_POWER_DOWN (0xffff)
|
||||
|
||||
#define DIB3000MC_REG_CLK_CFG_2 ( 1032)
|
||||
#define DIB3000MC_CLK_CFG_2_PUP_FIXED (0x012c)
|
||||
#define DIB3000MC_CLK_CFG_2_PUP_PORT (0x0104)
|
||||
#define DIB3000MC_CLK_CFG_2_PUP_MOBILE (0x0000)
|
||||
#define DIB3000MC_CLK_CFG_2_POWER_DOWN (0xffff)
|
||||
|
||||
#define DIB3000MC_REG_CLK_CFG_3 ( 1033)
|
||||
#define DIB3000MC_CLK_CFG_3_POWER_UP ( 0)
|
||||
#define DIB3000MC_CLK_CFG_3_POWER_DOWN (0xfff5)
|
||||
|
||||
#define DIB3000MC_REG_CLK_CFG_7 ( 1037)
|
||||
#define DIB3000MC_CLK_CFG_7_INIT ( 12592)
|
||||
#define DIB3000MC_CLK_CFG_7_POWER_UP (~0x0003)
|
||||
#define DIB3000MC_CLK_CFG_7_PWR_DOWN (0x0003)
|
||||
#define DIB3000MC_CLK_CFG_7_DIV_IN_OFF (1 << 8)
|
||||
|
||||
/* was commented out ??? */
|
||||
#define DIB3000MC_REG_CLK_CFG_8 ( 1038)
|
||||
#define DIB3000MC_CLK_CFG_8_POWER_UP (0x160c)
|
||||
|
||||
#define DIB3000MC_REG_CLK_CFG_9 ( 1039)
|
||||
#define DIB3000MC_CLK_CFG_9_POWER_UP ( 0)
|
||||
|
||||
/* also clock ??? */
|
||||
#define DIB3000MC_REG_ELEC_OUT ( 1040)
|
||||
#define DIB3000MC_ELEC_OUT_HIGH_Z ( 0)
|
||||
#define DIB3000MC_ELEC_OUT_DIV_OUT_ON ( 1)
|
||||
#define DIB3000MC_ELEC_OUT_SLAVE ( 3)
|
||||
|
||||
#endif
|
||||
|
|
@ -32,7 +32,7 @@
|
|||
#include "mt2060.h"
|
||||
#include "mt2060_priv.h"
|
||||
|
||||
static int debug=0;
|
||||
static int debug;
|
||||
module_param(debug, int, 0644);
|
||||
MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
|
||||
|
||||
|
|
@ -350,7 +350,7 @@ int mt2060_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt206
|
|||
kfree(priv);
|
||||
return -ENODEV;
|
||||
}
|
||||
printk(KERN_INFO "MT2060: successfully identified\n");
|
||||
printk(KERN_INFO "MT2060: successfully identified (IF1 = %d)\n", if1);
|
||||
memcpy(&fe->ops.tuner_ops, &mt2060_tuner_ops, sizeof(struct dvb_tuner_ops));
|
||||
|
||||
fe->tuner_priv = priv;
|
||||
|
|
|
|||
Loading…
Reference in New Issue