ARM: dts: dra72-evm-revc: add phy impedance settings
The default impedance settings of the phy is not the optimal value, due to this the second ethernet is not working. Fix it with correct values which makes the second ethernet port to work. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
ed838fe937
commit
b76db38cd8
|
@ -62,6 +62,7 @@
|
||||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
|
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
|
||||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
|
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
|
||||||
|
ti,min-output-impedance;
|
||||||
};
|
};
|
||||||
|
|
||||||
dp83867_1: ethernet-phy@3 {
|
dp83867_1: ethernet-phy@3 {
|
||||||
|
@ -69,5 +70,6 @@
|
||||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
|
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
|
||||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
|
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
|
||||||
|
ti,min-output-imepdance;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
Loading…
Reference in New Issue