clk: socfpga: Fix the smplsel on Arria10 and Stratix10
The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are
offset by 1 additional bit.
Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and
Stratix10 platforms.
Fixes: 5611a5ba8e
("clk: socfpga: update clk.h so for Arria10 platform to use")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
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@ -86,7 +86,7 @@ static int socfpga_clk_prepare(struct clk_hw *hwclk)
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}
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}
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}
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}
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hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
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hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]);
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if (!IS_ERR(socfpgaclk->sys_mgr_base_addr))
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if (!IS_ERR(socfpgaclk->sys_mgr_base_addr))
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regmap_write(socfpgaclk->sys_mgr_base_addr,
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regmap_write(socfpgaclk->sys_mgr_base_addr,
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SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing);
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SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing);
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@ -32,6 +32,9 @@
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#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
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#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
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((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
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((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
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#define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \
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((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0))
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extern void __iomem *clk_mgr_base_addr;
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extern void __iomem *clk_mgr_base_addr;
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extern void __iomem *clk_mgr_a10_base_addr;
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extern void __iomem *clk_mgr_a10_base_addr;
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