drm/amd/powerplay: correct UVD/VCE PG state on custom pptable uploading
[ Upstream commit 2c5b8080d8
]
The UVD/VCE PG state is managed by UVD and VCE IP. It's error-prone to
assume the bootup state in SMU based on the dpm status.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -1640,12 +1640,6 @@ static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
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data->uvd_power_gated = true;
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data->vce_power_gated = true;
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if (data->smu_features[GNLD_DPM_UVD].enabled)
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data->uvd_power_gated = false;
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if (data->smu_features[GNLD_DPM_VCE].enabled)
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data->vce_power_gated = false;
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}
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static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
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