MIPS: Whitespace cleanups and reformatting.
Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <sjhill@mips.com> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4781/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -1142,17 +1142,21 @@ do { \
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/*
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* Macros to access the floating point coprocessor control registers
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*/
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#define read_32bit_cp1_register(source) \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tpush\n\t" \
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".set\treorder\n\t" \
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/* gas fails to assemble cfc1 for some archs (octeon).*/ \
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".set\tmips1\n\t" \
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"cfc1\t%0,"STR(source)"\n\t" \
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".set\tpop" \
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: "=r" (__res)); \
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__res;})
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#define read_32bit_cp1_register(source) \
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({ \
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int __res; \
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\
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__asm__ __volatile__( \
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" .set push \n" \
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" .set reorder \n" \
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" # gas fails to assemble cfc1 for some archs, \n" \
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" # like Octeon. \n" \
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" .set mips1 \n" \
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" cfc1 %0,"STR(source)" \n" \
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" .set pop \n" \
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: "=r" (__res)); \
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__res; \
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})
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#define rddsp(mask) \
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({ \
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@ -518,7 +518,7 @@ static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
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offset >>= 16;
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vaddr = (unsigned long __user *)
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((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
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((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
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if ((unsigned long)vaddr & 3)
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return SIGBUS;
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@ -558,7 +558,7 @@ static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
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offset >>= 16;
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vaddr = (unsigned long __user *)
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((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
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((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
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reg = (opcode & RT) >> 16;
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if ((unsigned long)vaddr & 3)
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