Samsung exynos clock related DT updates for v3.15
- use macros instead of hard coded numbers for clock bindings NOTE: this is based on v3.15-next/dt-samsung -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJTE9QWAAoJEA0Cl+kVi2xqDBAQAJORPoEBQOs+Y2vHughs16jg 48uG6ttIFcjo9HRe0DVpEBE4gyQzIUGOgU/8ebU29kA2Ce0calTQZDZZ4YQZ1LXL zc1MACqS2LBKoeFFCpyq61ghtNWjTyoQCgkQi6C/GNUv36uEuIAUPD5Cj+j5eUfS M6bHImxE0sHFxYzZPQ3BGO0gN7IoPEGYrXJmgD5LbswBgYP3qbFckr/spGzKb0Yt LyLTiZzb03l9C8lpaRkzA6AzAUJSqH2ialD7cEIVgxG1/Zmx0p2fW0ORpXWoU4Tp vM7akP4ZkdDdW5fUZOVklzjxnBG3pKOXivOeZ28K66vS3u5RRJYHd7gq4/d77JUe Jzz6s3jmr5Rk5UVtqrPNqu7SRz8RR9j5MBJ2gKDJK4GVelGqk8KgWdfAF/BGzGdj FbZMh3TzPMJxrcLTNDDaBrawg/mxQifV2ixV3hHFUtjw6Bbocxo5NDmG2sol8zQU XI7IlFzTQzqkb5KLYfPS3OGfBAvLUXfe9XT/XJkrSVYHXj7DJEonbZlTrxp35HYA 0bFacDXMMqwqqaGjMsAbIslq0QUNBU97ztmmwInYfrBwah1nO3QxDhfATRF3VrHa 264vnh1l97uWjN/iwTXMeZC6+ng2KqmQvrIbXc4d02buVRcnDIY+v5M11CY1AUFt Sz112ddWErQHi2MQoEJ0 =4qfh -----END PGP SIGNATURE----- Merge tag 'exynos-clk' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt Samsung exynos clock related DT updates for v3.15 from Kukjim Kim: - use macros instead of hard coded numbers for clock bindings NOTE: this is based on v3.15-next/dt-samsung * tag 'exynos-clk' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: dts: use macros in clock bindings for exynos5440 ARM: dts: use macros in clock bindings for exynos5420 ARM: dts: use macros in clock bindings for exynos5250 ARM: dts: use macros in clock bindings for exynos4
This commit is contained in:
Olof Johansson
commit
b989e36aaa
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@ -15,259 +15,12 @@ Required Properties:
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- #clock-cells: should be 1.
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The following is the list of clocks generated by the controller. Each clock is
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assigned an identifier and client nodes use this identifier to specify the
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clock which they consume. Some of the clocks are available only on a particular
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Exynos4 SoC and this is specified where applicable.
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[Core Clocks]
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Clock ID SoC (if specific)
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-----------------------------------------------
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xxti 1
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xusbxti 2
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fin_pll 3
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fout_apll 4
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fout_mpll 5
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fout_epll 6
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fout_vpll 7
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sclk_apll 8
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sclk_mpll 9
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sclk_epll 10
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sclk_vpll 11
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arm_clk 12
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aclk200 13
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aclk100 14
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aclk160 15
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aclk133 16
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mout_mpll_user_t 17 Exynos4x12
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mout_mpll_user_c 18 Exynos4x12
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mout_core 19
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mout_apll 20
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[Clock Gate for Special Clocks]
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Clock ID SoC (if specific)
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-----------------------------------------------
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sclk_fimc0 128
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sclk_fimc1 129
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sclk_fimc2 130
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sclk_fimc3 131
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sclk_cam0 132
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sclk_cam1 133
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sclk_csis0 134
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sclk_csis1 135
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sclk_hdmi 136
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sclk_mixer 137
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sclk_dac 138
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sclk_pixel 139
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sclk_fimd0 140
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sclk_mdnie0 141 Exynos4412
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sclk_mdnie_pwm0 12 142 Exynos4412
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sclk_mipi0 143
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sclk_audio0 144
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sclk_mmc0 145
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sclk_mmc1 146
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sclk_mmc2 147
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sclk_mmc3 148
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sclk_mmc4 149
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sclk_sata 150 Exynos4210
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sclk_uart0 151
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sclk_uart1 152
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sclk_uart2 153
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sclk_uart3 154
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sclk_uart4 155
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sclk_audio1 156
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sclk_audio2 157
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sclk_spdif 158
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sclk_spi0 159
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sclk_spi1 160
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sclk_spi2 161
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sclk_slimbus 162
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sclk_fimd1 163 Exynos4210
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sclk_mipi1 164 Exynos4210
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sclk_pcm1 165
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sclk_pcm2 166
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sclk_i2s1 167
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sclk_i2s2 168
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sclk_mipihsi 169 Exynos4412
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sclk_mfc 170
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sclk_pcm0 171
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sclk_g3d 172
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sclk_pwm_isp 173 Exynos4x12
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sclk_spi0_isp 174 Exynos4x12
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sclk_spi1_isp 175 Exynos4x12
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sclk_uart_isp 176 Exynos4x12
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sclk_fimg2d 177
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[Peripheral Clock Gates]
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Clock ID SoC (if specific)
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-----------------------------------------------
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fimc0 256
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fimc1 257
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fimc2 258
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fimc3 259
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csis0 260
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csis1 261
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jpeg 262
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smmu_fimc0 263
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smmu_fimc1 264
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smmu_fimc2 265
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smmu_fimc3 266
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smmu_jpeg 267
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vp 268
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mixer 269
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tvenc 270 Exynos4210
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hdmi 271
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smmu_tv 272
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mfc 273
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smmu_mfcl 274
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smmu_mfcr 275
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g3d 276
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g2d 277
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rotator 278 Exynos4210
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mdma 279 Exynos4210
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smmu_g2d 280 Exynos4210
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smmu_rotator 281 Exynos4210
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smmu_mdma 282 Exynos4210
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fimd0 283
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mie0 284
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mdnie0 285 Exynos4412
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dsim0 286
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smmu_fimd0 287
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fimd1 288 Exynos4210
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mie1 289 Exynos4210
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dsim1 290 Exynos4210
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smmu_fimd1 291 Exynos4210
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pdma0 292
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pdma1 293
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pcie_phy 294
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sata_phy 295 Exynos4210
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tsi 296
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sdmmc0 297
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sdmmc1 298
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sdmmc2 299
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sdmmc3 300
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sdmmc4 301
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sata 302 Exynos4210
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sromc 303
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usb_host 304
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usb_device 305
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pcie 306
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onenand 307
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nfcon 308
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smmu_pcie 309
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gps 310
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smmu_gps 311
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uart0 312
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uart1 313
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uart2 314
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uart3 315
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uart4 316
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i2c0 317
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i2c1 318
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i2c2 319
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i2c3 320
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i2c4 321
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i2c5 322
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i2c6 323
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i2c7 324
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i2c_hdmi 325
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tsadc 326
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spi0 327
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spi1 328
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spi2 329
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i2s1 330
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i2s2 331
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pcm0 332
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i2s0 333
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pcm1 334
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pcm2 335
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pwm 336
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slimbus 337
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spdif 338
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ac97 339
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modemif 340
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chipid 341
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sysreg 342
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hdmi_cec 343
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mct 344
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wdt 345
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rtc 346
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keyif 347
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audss 348
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mipi_hsi 349 Exynos4210
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mdma2 350 Exynos4210
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pixelasyncm0 351
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pixelasyncm1 352
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fimc_lite0 353 Exynos4x12
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fimc_lite1 354 Exynos4x12
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ppmuispx 355 Exynos4x12
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ppmuispmx 356 Exynos4x12
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fimc_isp 357 Exynos4x12
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fimc_drc 358 Exynos4x12
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fimc_fd 359 Exynos4x12
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mcuisp 360 Exynos4x12
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gicisp 361 Exynos4x12
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smmu_isp 362 Exynos4x12
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smmu_drc 363 Exynos4x12
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smmu_fd 364 Exynos4x12
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smmu_lite0 365 Exynos4x12
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smmu_lite1 366 Exynos4x12
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mcuctl_isp 367 Exynos4x12
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mpwm_isp 368 Exynos4x12
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i2c0_isp 369 Exynos4x12
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i2c1_isp 370 Exynos4x12
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mtcadc_isp 371 Exynos4x12
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pwm_isp 372 Exynos4x12
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wdt_isp 373 Exynos4x12
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uart_isp 374 Exynos4x12
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asyncaxim 375 Exynos4x12
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smmu_ispcx 376 Exynos4x12
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spi0_isp 377 Exynos4x12
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spi1_isp 378 Exynos4x12
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pwm_isp_sclk 379 Exynos4x12
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spi0_isp_sclk 380 Exynos4x12
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spi1_isp_sclk 381 Exynos4x12
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uart_isp_sclk 382 Exynos4x12
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tmu_apbif 383
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[Mux Clocks]
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Clock ID SoC (if specific)
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-----------------------------------------------
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mout_fimc0 384
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mout_fimc1 385
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mout_fimc2 386
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mout_fimc3 387
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mout_cam0 388
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mout_cam1 389
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mout_csis0 390
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mout_csis1 391
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mout_g3d0 392
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mout_g3d1 393
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mout_g3d 394
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aclk400_mcuisp 395 Exynos4x12
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[Div Clocks]
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Clock ID SoC (if specific)
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-----------------------------------------------
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div_isp0 450 Exynos4x12
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div_isp1 451 Exynos4x12
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div_mcuisp0 452 Exynos4x12
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div_mcuisp1 453 Exynos4x12
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div_aclk200 454 Exynos4x12
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div_aclk400_mcuisp 455 Exynos4x12
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume.
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All available clocks are defined as preprocessor macros in
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dt-bindings/clock/exynos4.h header and can be used in device
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tree sources.
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Example 1: An example of a clock controller node is listed below.
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@ -285,6 +38,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
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compatible = "samsung,exynos4210-uart";
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reg = <0x13820000 0x100>;
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interrupts = <0 54 0>;
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clocks = <&clock 314>, <&clock 153>;
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clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
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clock-names = "uart", "clk_uart_baud0";
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};
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@ -13,163 +13,12 @@ Required Properties:
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- #clock-cells: should be 1.
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The following is the list of clocks generated by the controller. Each clock is
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assigned an identifier and client nodes use this identifier to specify the
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clock which they consume.
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[Core Clocks]
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Clock ID
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----------------------------
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fin_pll 1
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[Clock Gate for Special Clocks]
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Clock ID
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----------------------------
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sclk_cam_bayer 128
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sclk_cam0 129
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sclk_cam1 130
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sclk_gscl_wa 131
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sclk_gscl_wb 132
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sclk_fimd1 133
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sclk_mipi1 134
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sclk_dp 135
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sclk_hdmi 136
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sclk_pixel 137
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sclk_audio0 138
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sclk_mmc0 139
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sclk_mmc1 140
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sclk_mmc2 141
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sclk_mmc3 142
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sclk_sata 143
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sclk_usb3 144
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sclk_jpeg 145
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sclk_uart0 146
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sclk_uart1 147
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sclk_uart2 148
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sclk_uart3 149
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sclk_pwm 150
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sclk_audio1 151
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sclk_audio2 152
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sclk_spdif 153
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sclk_spi0 154
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sclk_spi1 155
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sclk_spi2 156
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div_i2s1 157
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div_i2s2 158
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sclk_hdmiphy 159
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div_pcm0 160
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[Peripheral Clock Gates]
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Clock ID
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----------------------------
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gscl0 256
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gscl1 257
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gscl2 258
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gscl3 259
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gscl_wa 260
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gscl_wb 261
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smmu_gscl0 262
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smmu_gscl1 263
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smmu_gscl2 264
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smmu_gscl3 265
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mfc 266
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smmu_mfcl 267
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smmu_mfcr 268
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rotator 269
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jpeg 270
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mdma1 271
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smmu_rotator 272
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smmu_jpeg 273
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smmu_mdma1 274
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pdma0 275
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pdma1 276
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sata 277
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usbotg 278
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mipi_hsi 279
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sdmmc0 280
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sdmmc1 281
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sdmmc2 282
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sdmmc3 283
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sromc 284
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usb2 285
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usb3 286
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sata_phyctrl 287
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sata_phyi2c 288
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uart0 289
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uart1 290
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uart2 291
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uart3 292
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uart4 293
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i2c0 294
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i2c1 295
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i2c2 296
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i2c3 297
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i2c4 298
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i2c5 299
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i2c6 300
|
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i2c7 301
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i2c_hdmi 302
|
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adc 303
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spi0 304
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spi1 305
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spi2 306
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i2s1 307
|
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i2s2 308
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pcm1 309
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pcm2 310
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pwm 311
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spdif 312
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ac97 313
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hsi2c0 314
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hsi2c1 315
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hs12c2 316
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hs12c3 317
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chipid 318
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sysreg 319
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pmu 320
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cmu_top 321
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cmu_core 322
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cmu_mem 323
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tzpc0 324
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tzpc1 325
|
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tzpc2 326
|
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tzpc3 327
|
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tzpc4 328
|
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tzpc5 329
|
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tzpc6 330
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tzpc7 331
|
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tzpc8 332
|
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tzpc9 333
|
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hdmi_cec 334
|
||||
mct 335
|
||||
wdt 336
|
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rtc 337
|
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tmu 338
|
||||
fimd1 339
|
||||
mie1 340
|
||||
dsim0 341
|
||||
dp 342
|
||||
mixer 343
|
||||
hdmi 344
|
||||
g2d 345
|
||||
mdma0 346
|
||||
smmu_mdma0 347
|
||||
|
||||
|
||||
[Clock Muxes]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
mout_hdmi 1024
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos5250.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
|
|
@ -187,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 314>, <&clock 153>;
|
||||
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -13,184 +13,12 @@ Required Properties:
|
|||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
The following is the list of clocks generated by the controller. Each clock is
|
||||
assigned an identifier and client nodes use this identifier to specify the
|
||||
clock which they consume.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
|
||||
[Core Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
fin_pll 1
|
||||
|
||||
[Clock Gate for Special Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
sclk_uart0 128
|
||||
sclk_uart1 129
|
||||
sclk_uart2 130
|
||||
sclk_uart3 131
|
||||
sclk_mmc0 132
|
||||
sclk_mmc1 133
|
||||
sclk_mmc2 134
|
||||
sclk_spi0 135
|
||||
sclk_spi1 136
|
||||
sclk_spi2 137
|
||||
sclk_i2s1 138
|
||||
sclk_i2s2 139
|
||||
sclk_pcm1 140
|
||||
sclk_pcm2 141
|
||||
sclk_spdif 142
|
||||
sclk_hdmi 143
|
||||
sclk_pixel 144
|
||||
sclk_dp1 145
|
||||
sclk_mipi1 146
|
||||
sclk_fimd1 147
|
||||
sclk_maudio0 148
|
||||
sclk_maupcm0 149
|
||||
sclk_usbd300 150
|
||||
sclk_usbd301 151
|
||||
sclk_usbphy300 152
|
||||
sclk_usbphy301 153
|
||||
sclk_unipro 154
|
||||
sclk_pwm 155
|
||||
sclk_gscl_wa 156
|
||||
sclk_gscl_wb 157
|
||||
sclk_hdmiphy 158
|
||||
|
||||
[Peripheral Clock Gates]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
aclk66_peric 256
|
||||
uart0 257
|
||||
uart1 258
|
||||
uart2 259
|
||||
uart3 260
|
||||
i2c0 261
|
||||
i2c1 262
|
||||
i2c2 263
|
||||
i2c3 264
|
||||
i2c4 265
|
||||
i2c5 266
|
||||
i2c6 267
|
||||
i2c7 268
|
||||
i2c_hdmi 269
|
||||
tsadc 270
|
||||
spi0 271
|
||||
spi1 272
|
||||
spi2 273
|
||||
keyif 274
|
||||
i2s1 275
|
||||
i2s2 276
|
||||
pcm1 277
|
||||
pcm2 278
|
||||
pwm 279
|
||||
spdif 280
|
||||
i2c8 281
|
||||
i2c9 282
|
||||
i2c10 283
|
||||
aclk66_psgen 300
|
||||
chipid 301
|
||||
sysreg 302
|
||||
tzpc0 303
|
||||
tzpc1 304
|
||||
tzpc2 305
|
||||
tzpc3 306
|
||||
tzpc4 307
|
||||
tzpc5 308
|
||||
tzpc6 309
|
||||
tzpc7 310
|
||||
tzpc8 311
|
||||
tzpc9 312
|
||||
hdmi_cec 313
|
||||
seckey 314
|
||||
mct 315
|
||||
wdt 316
|
||||
rtc 317
|
||||
tmu 318
|
||||
tmu_gpu 319
|
||||
pclk66_gpio 330
|
||||
aclk200_fsys2 350
|
||||
mmc0 351
|
||||
mmc1 352
|
||||
mmc2 353
|
||||
sromc 354
|
||||
ufs 355
|
||||
aclk200_fsys 360
|
||||
tsi 361
|
||||
pdma0 362
|
||||
pdma1 363
|
||||
rtic 364
|
||||
usbh20 365
|
||||
usbd300 366
|
||||
usbd301 377
|
||||
aclk400_mscl 380
|
||||
mscl0 381
|
||||
mscl1 382
|
||||
mscl2 383
|
||||
smmu_mscl0 384
|
||||
smmu_mscl1 385
|
||||
smmu_mscl2 386
|
||||
aclk333 400
|
||||
mfc 401
|
||||
smmu_mfcl 402
|
||||
smmu_mfcr 403
|
||||
aclk200_disp1 410
|
||||
dsim1 411
|
||||
dp1 412
|
||||
hdmi 413
|
||||
aclk300_disp1 420
|
||||
fimd1 421
|
||||
smmu_fimd1 422
|
||||
aclk166 430
|
||||
mixer 431
|
||||
aclk266 440
|
||||
rotator 441
|
||||
mdma1 442
|
||||
smmu_rotator 443
|
||||
smmu_mdma1 444
|
||||
aclk300_jpeg 450
|
||||
jpeg 451
|
||||
jpeg2 452
|
||||
smmu_jpeg 453
|
||||
aclk300_gscl 460
|
||||
smmu_gscl0 461
|
||||
smmu_gscl1 462
|
||||
gscl_wa 463
|
||||
gscl_wb 464
|
||||
gscl0 465
|
||||
gscl1 466
|
||||
clk_3aa 467
|
||||
aclk266_g2d 470
|
||||
sss 471
|
||||
slim_sss 472
|
||||
mdma0 473
|
||||
aclk333_g2d 480
|
||||
g2d 481
|
||||
aclk333_432_gscl 490
|
||||
smmu_3aa 491
|
||||
smmu_fimcl0 492
|
||||
smmu_fimcl1 493
|
||||
smmu_fimcl3 494
|
||||
fimc_lite3 495
|
||||
aclk_g3d 500
|
||||
g3d 501
|
||||
smmu_mixer 502
|
||||
|
||||
Mux ID
|
||||
----------------------------
|
||||
|
||||
mout_hdmi 640
|
||||
|
||||
Divider ID
|
||||
----------------------------
|
||||
|
||||
dout_pixel 768
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos5420.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
|
|
@ -208,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 259>, <&clock 130>;
|
||||
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -12,45 +12,12 @@ Required Properties:
|
|||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
The following is the list of clocks generated by the controller. Each clock is
|
||||
assigned an identifier and client nodes use this identifier to specify the
|
||||
clock which they consume.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
|
||||
[Core Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
xtal 1
|
||||
arm_clk 2
|
||||
|
||||
[Peripheral Clock Gates]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
spi_baud 16
|
||||
pb0_250 17
|
||||
pr0_250 18
|
||||
pr1_250 19
|
||||
b_250 20
|
||||
b_125 21
|
||||
b_200 22
|
||||
sata 23
|
||||
usb 24
|
||||
gmac0 25
|
||||
cs250 26
|
||||
pb0_250_o 27
|
||||
pr0_250_o 28
|
||||
pr1_250_o 29
|
||||
b_250_o 30
|
||||
b_125_o 31
|
||||
b_200_o 32
|
||||
sata_o 33
|
||||
usb_o 34
|
||||
gmac0_o 35
|
||||
cs250_o 36
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos5440.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Example: An example of a clock controller node is listed below.
|
||||
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/exynos4.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
@ -119,7 +120,7 @@
|
|||
compatible = "samsung,exynos4210-fimc";
|
||||
reg = <0x11800000 0x1000>;
|
||||
interrupts = <0 84 0>;
|
||||
clocks = <&clock 256>, <&clock 128>;
|
||||
clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
|
||||
clock-names = "fimc", "sclk_fimc";
|
||||
samsung,power-domain = <&pd_cam>;
|
||||
samsung,sysreg = <&sys_reg>;
|
||||
|
|
@ -130,7 +131,7 @@
|
|||
compatible = "samsung,exynos4210-fimc";
|
||||
reg = <0x11810000 0x1000>;
|
||||
interrupts = <0 85 0>;
|
||||
clocks = <&clock 257>, <&clock 129>;
|
||||
clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
|
||||
clock-names = "fimc", "sclk_fimc";
|
||||
samsung,power-domain = <&pd_cam>;
|
||||
samsung,sysreg = <&sys_reg>;
|
||||
|
|
@ -141,7 +142,7 @@
|
|||
compatible = "samsung,exynos4210-fimc";
|
||||
reg = <0x11820000 0x1000>;
|
||||
interrupts = <0 86 0>;
|
||||
clocks = <&clock 258>, <&clock 130>;
|
||||
clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
|
||||
clock-names = "fimc", "sclk_fimc";
|
||||
samsung,power-domain = <&pd_cam>;
|
||||
samsung,sysreg = <&sys_reg>;
|
||||
|
|
@ -152,7 +153,7 @@
|
|||
compatible = "samsung,exynos4210-fimc";
|
||||
reg = <0x11830000 0x1000>;
|
||||
interrupts = <0 87 0>;
|
||||
clocks = <&clock 259>, <&clock 131>;
|
||||
clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
|
||||
clock-names = "fimc", "sclk_fimc";
|
||||
samsung,power-domain = <&pd_cam>;
|
||||
samsung,sysreg = <&sys_reg>;
|
||||
|
|
@ -163,7 +164,7 @@
|
|||
compatible = "samsung,exynos4210-csis";
|
||||
reg = <0x11880000 0x4000>;
|
||||
interrupts = <0 78 0>;
|
||||
clocks = <&clock 260>, <&clock 134>;
|
||||
clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
|
||||
clock-names = "csis", "sclk_csis";
|
||||
bus-width = <4>;
|
||||
samsung,power-domain = <&pd_cam>;
|
||||
|
|
@ -178,7 +179,7 @@
|
|||
compatible = "samsung,exynos4210-csis";
|
||||
reg = <0x11890000 0x4000>;
|
||||
interrupts = <0 80 0>;
|
||||
clocks = <&clock 261>, <&clock 135>;
|
||||
clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
|
||||
clock-names = "csis", "sclk_csis";
|
||||
bus-width = <2>;
|
||||
samsung,power-domain = <&pd_cam>;
|
||||
|
|
@ -194,7 +195,7 @@
|
|||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x10060000 0x100>;
|
||||
interrupts = <0 43 0>;
|
||||
clocks = <&clock 345>;
|
||||
clocks = <&clock CLK_WDT>;
|
||||
clock-names = "watchdog";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -203,7 +204,7 @@
|
|||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x10070000 0x100>;
|
||||
interrupts = <0 44 0>, <0 45 0>;
|
||||
clocks = <&clock 346>;
|
||||
clocks = <&clock CLK_RTC>;
|
||||
clock-names = "rtc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -212,7 +213,7 @@
|
|||
compatible = "samsung,s5pv210-keypad";
|
||||
reg = <0x100A0000 0x100>;
|
||||
interrupts = <0 109 0>;
|
||||
clocks = <&clock 347>;
|
||||
clocks = <&clock CLK_KEYIF>;
|
||||
clock-names = "keypad";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -221,7 +222,7 @@
|
|||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12510000 0x100>;
|
||||
interrupts = <0 73 0>;
|
||||
clocks = <&clock 297>, <&clock 145>;
|
||||
clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -230,7 +231,7 @@
|
|||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12520000 0x100>;
|
||||
interrupts = <0 74 0>;
|
||||
clocks = <&clock 298>, <&clock 146>;
|
||||
clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -239,7 +240,7 @@
|
|||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12530000 0x100>;
|
||||
interrupts = <0 75 0>;
|
||||
clocks = <&clock 299>, <&clock 147>;
|
||||
clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -248,7 +249,7 @@
|
|||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12540000 0x100>;
|
||||
interrupts = <0 76 0>;
|
||||
clocks = <&clock 300>, <&clock 148>;
|
||||
clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -257,7 +258,7 @@
|
|||
compatible = "samsung,exynos4210-ehci";
|
||||
reg = <0x12580000 0x100>;
|
||||
interrupts = <0 70 0>;
|
||||
clocks = <&clock 304>;
|
||||
clocks = <&clock CLK_USB_HOST>;
|
||||
clock-names = "usbhost";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -266,7 +267,7 @@
|
|||
compatible = "samsung,exynos4210-ohci";
|
||||
reg = <0x12590000 0x100>;
|
||||
interrupts = <0 70 0>;
|
||||
clocks = <&clock 304>;
|
||||
clocks = <&clock CLK_USB_HOST>;
|
||||
clock-names = "usbhost";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -276,7 +277,7 @@
|
|||
reg = <0x13400000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
samsung,power-domain = <&pd_mfc>;
|
||||
clocks = <&clock 273>;
|
||||
clocks = <&clock CLK_MFC>;
|
||||
clock-names = "mfc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -285,7 +286,7 @@
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13800000 0x100>;
|
||||
interrupts = <0 52 0>;
|
||||
clocks = <&clock 312>, <&clock 151>;
|
||||
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -294,7 +295,7 @@
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13810000 0x100>;
|
||||
interrupts = <0 53 0>;
|
||||
clocks = <&clock 313>, <&clock 152>;
|
||||
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -303,7 +304,7 @@
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 314>, <&clock 153>;
|
||||
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -312,7 +313,7 @@
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13830000 0x100>;
|
||||
interrupts = <0 55 0>;
|
||||
clocks = <&clock 315>, <&clock 154>;
|
||||
clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -323,7 +324,7 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13860000 0x100>;
|
||||
interrupts = <0 58 0>;
|
||||
clocks = <&clock 317>;
|
||||
clocks = <&clock CLK_I2C0>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_bus>;
|
||||
|
|
@ -336,7 +337,7 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13870000 0x100>;
|
||||
interrupts = <0 59 0>;
|
||||
clocks = <&clock 318>;
|
||||
clocks = <&clock CLK_I2C1>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_bus>;
|
||||
|
|
@ -349,7 +350,7 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13880000 0x100>;
|
||||
interrupts = <0 60 0>;
|
||||
clocks = <&clock 319>;
|
||||
clocks = <&clock CLK_I2C2>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -360,7 +361,7 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13890000 0x100>;
|
||||
interrupts = <0 61 0>;
|
||||
clocks = <&clock 320>;
|
||||
clocks = <&clock CLK_I2C3>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -371,7 +372,7 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138A0000 0x100>;
|
||||
interrupts = <0 62 0>;
|
||||
clocks = <&clock 321>;
|
||||
clocks = <&clock CLK_I2C4>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -382,7 +383,7 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138B0000 0x100>;
|
||||
interrupts = <0 63 0>;
|
||||
clocks = <&clock 322>;
|
||||
clocks = <&clock CLK_I2C5>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -393,7 +394,7 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138C0000 0x100>;
|
||||
interrupts = <0 64 0>;
|
||||
clocks = <&clock 323>;
|
||||
clocks = <&clock CLK_I2C6>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -404,7 +405,7 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138D0000 0x100>;
|
||||
interrupts = <0 65 0>;
|
||||
clocks = <&clock 324>;
|
||||
clocks = <&clock CLK_I2C7>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -417,7 +418,7 @@
|
|||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 327>, <&clock 159>;
|
||||
clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_bus>;
|
||||
|
|
@ -432,7 +433,7 @@
|
|||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 328>, <&clock 160>;
|
||||
clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_bus>;
|
||||
|
|
@ -447,7 +448,7 @@
|
|||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 329>, <&clock 161>;
|
||||
clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_bus>;
|
||||
|
|
@ -458,7 +459,7 @@
|
|||
compatible = "samsung,exynos4210-pwm";
|
||||
reg = <0x139D0000 0x1000>;
|
||||
interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
|
||||
clocks = <&clock 336>;
|
||||
clocks = <&clock CLK_PWM>;
|
||||
clock-names = "timers";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
|
|
@ -475,7 +476,7 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12680000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
clocks = <&clock 292>;
|
||||
clocks = <&clock CLK_PDMA0>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
|
|
@ -486,7 +487,7 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12690000 0x1000>;
|
||||
interrupts = <0 36 0>;
|
||||
clocks = <&clock 293>;
|
||||
clocks = <&clock CLK_PDMA1>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
|
|
@ -497,7 +498,7 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12850000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
clocks = <&clock 279>;
|
||||
clocks = <&clock CLK_MDMA>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
|
|
@ -511,7 +512,7 @@
|
|||
reg = <0x11c00000 0x20000>;
|
||||
interrupt-names = "fifo", "vsync", "lcd_sys";
|
||||
interrupts = <11 0>, <11 1>, <11 2>;
|
||||
clocks = <&clock 140>, <&clock 283>;
|
||||
clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
|
||||
clock-names = "sclk_fimd", "fimd";
|
||||
samsung,power-domain = <&pd_lcd0>;
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@
|
|||
reg = <0x10050000 0x800>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
|
||||
clocks = <&clock 3>, <&clock 344>;
|
||||
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
|
||||
mct_map: mct-map {
|
||||
|
|
@ -109,7 +109,7 @@
|
|||
interrupt-parent = <&combiner>;
|
||||
reg = <0x100C0000 0x100>;
|
||||
interrupts = <2 4>;
|
||||
clocks = <&clock 383>;
|
||||
clocks = <&clock CLK_TMU_APBIF>;
|
||||
clock-names = "tmu_apbif";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -118,13 +118,14 @@
|
|||
compatible = "samsung,s5pv210-g2d";
|
||||
reg = <0x12800000 0x1000>;
|
||||
interrupts = <0 89 0>;
|
||||
clocks = <&clock 177>, <&clock 277>;
|
||||
clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
|
||||
clock-names = "sclk_fimg2d", "fimg2d";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
camera {
|
||||
clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>;
|
||||
clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
|
||||
<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
|
||||
clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
|
||||
|
||||
fimc_0: fimc@11800000 {
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@
|
|||
reg = <0x10050000 0x800>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0>, <1>, <2>, <3>, <4>;
|
||||
clocks = <&clock 3>, <&clock 344>;
|
||||
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
|
||||
mct_map: mct-map {
|
||||
|
|
@ -97,13 +97,14 @@
|
|||
compatible = "samsung,exynos4212-g2d";
|
||||
reg = <0x10800000 0x1000>;
|
||||
interrupts = <0 89 0>;
|
||||
clocks = <&clock 177>, <&clock 277>;
|
||||
clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
|
||||
clock-names = "sclk_fimg2d", "fimg2d";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
camera {
|
||||
clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>;
|
||||
clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
|
||||
<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
|
||||
clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
|
||||
|
||||
fimc_0: fimc@11800000 {
|
||||
|
|
@ -145,7 +146,7 @@
|
|||
reg = <0x12390000 0x1000>;
|
||||
interrupts = <0 105 0>;
|
||||
samsung,power-domain = <&pd_isp>;
|
||||
clocks = <&clock 353>;
|
||||
clocks = <&clock CLK_FIMC_LITE0>;
|
||||
clock-names = "flite";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -155,7 +156,7 @@
|
|||
reg = <0x123A0000 0x1000>;
|
||||
interrupts = <0 106 0>;
|
||||
samsung,power-domain = <&pd_isp>;
|
||||
clocks = <&clock 354>;
|
||||
clocks = <&clock CLK_FIMC_LITE1>;
|
||||
clock-names = "flite";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -165,12 +166,19 @@
|
|||
reg = <0x12000000 0x260000>;
|
||||
interrupts = <0 90 0>, <0 95 0>;
|
||||
samsung,power-domain = <&pd_isp>;
|
||||
clocks = <&clock 353>, <&clock 354>, <&clock 355>,
|
||||
<&clock 356>, <&clock 17>, <&clock 357>,
|
||||
<&clock 358>, <&clock 359>, <&clock 360>,
|
||||
<&clock 450>,<&clock 451>, <&clock 452>,
|
||||
<&clock 453>, <&clock 176>, <&clock 13>,
|
||||
<&clock 454>, <&clock 395>, <&clock 455>;
|
||||
clocks = <&clock CLK_FIMC_LITE0>,
|
||||
<&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
|
||||
<&clock CLK_PPMUISPMX>,
|
||||
<&clock CLK_MOUT_MPLL_USER_T>,
|
||||
<&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
|
||||
<&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
|
||||
<&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
|
||||
<&clock CLK_DIV_MCUISP0>,
|
||||
<&clock CLK_DIV_MCUISP1>,
|
||||
<&clock CLK_SCLK_UART_ISP>,
|
||||
<&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
|
||||
<&clock CLK_ACLK400_MCUISP>,
|
||||
<&clock CLK_DIV_ACLK400_MCUISP>;
|
||||
clock-names = "lite0", "lite1", "ppmuispx",
|
||||
"ppmuispmx", "mpll", "isp",
|
||||
"drc", "fd", "mcuisp",
|
||||
|
|
@ -190,7 +198,7 @@
|
|||
i2c1_isp: i2c-isp@12140000 {
|
||||
compatible = "samsung,exynos4212-i2c-isp";
|
||||
reg = <0x12140000 0x100>;
|
||||
clocks = <&clock 370>;
|
||||
clocks = <&clock CLK_I2C1_ISP>;
|
||||
clock-names = "i2c_isp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -205,7 +213,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
fifo-depth = <0x80>;
|
||||
clocks = <&clock 301>, <&clock 149>;
|
||||
clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
|
||||
clock-names = "biu", "ciu";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/exynos5250.h>
|
||||
#include "exynos5.dtsi"
|
||||
#include "exynos5250-pinctrl.dtsi"
|
||||
|
||||
|
|
@ -90,7 +91,8 @@
|
|||
compatible = "samsung,exynos5250-audss-clock";
|
||||
reg = <0x03810000 0x0C>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>;
|
||||
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
|
||||
<&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
|
||||
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
|
||||
};
|
||||
|
||||
|
|
@ -115,7 +117,7 @@
|
|||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
clocks = <&clock 1>, <&clock 335>;
|
||||
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
|
||||
mct_map: mct-map {
|
||||
|
|
@ -176,7 +178,7 @@
|
|||
compatible = "samsung,exynos5250-wdt";
|
||||
reg = <0x101D0000 0x100>;
|
||||
interrupts = <0 42 0>;
|
||||
clocks = <&clock 336>;
|
||||
clocks = <&clock CLK_WDT>;
|
||||
clock-names = "watchdog";
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
};
|
||||
|
|
@ -185,7 +187,7 @@
|
|||
compatible = "samsung,exynos5250-g2d";
|
||||
reg = <0x10850000 0x1000>;
|
||||
interrupts = <0 91 0>;
|
||||
clocks = <&clock 345>;
|
||||
clocks = <&clock CLK_G2D>;
|
||||
clock-names = "fimg2d";
|
||||
};
|
||||
|
||||
|
|
@ -194,12 +196,12 @@
|
|||
reg = <0x11000000 0x10000>;
|
||||
interrupts = <0 96 0>;
|
||||
samsung,power-domain = <&pd_mfc>;
|
||||
clocks = <&clock 266>;
|
||||
clocks = <&clock CLK_MFC>;
|
||||
clock-names = "mfc";
|
||||
};
|
||||
|
||||
rtc@101E0000 {
|
||||
clocks = <&clock 337>;
|
||||
clocks = <&clock CLK_RTC>;
|
||||
clock-names = "rtc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -208,27 +210,27 @@
|
|||
compatible = "samsung,exynos5250-tmu";
|
||||
reg = <0x10060000 0x100>;
|
||||
interrupts = <0 65 0>;
|
||||
clocks = <&clock 338>;
|
||||
clocks = <&clock CLK_TMU>;
|
||||
clock-names = "tmu_apbif";
|
||||
};
|
||||
|
||||
serial@12C00000 {
|
||||
clocks = <&clock 289>, <&clock 146>;
|
||||
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C10000 {
|
||||
clocks = <&clock 290>, <&clock 147>;
|
||||
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C20000 {
|
||||
clocks = <&clock 291>, <&clock 148>;
|
||||
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C30000 {
|
||||
clocks = <&clock 292>, <&clock 149>;
|
||||
clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
|
|
@ -236,7 +238,7 @@
|
|||
compatible = "samsung,exynos5-sata-ahci";
|
||||
reg = <0x122F0000 0x1ff>;
|
||||
interrupts = <0 115 0>;
|
||||
clocks = <&clock 277>, <&clock 143>;
|
||||
clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
|
||||
clock-names = "sata", "sclk_sata";
|
||||
};
|
||||
|
||||
|
|
@ -251,7 +253,7 @@
|
|||
interrupts = <0 56 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 294>;
|
||||
clocks = <&clock CLK_I2C0>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_bus>;
|
||||
|
|
@ -264,7 +266,7 @@
|
|||
interrupts = <0 57 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 295>;
|
||||
clocks = <&clock CLK_I2C1>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_bus>;
|
||||
|
|
@ -277,7 +279,7 @@
|
|||
interrupts = <0 58 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 296>;
|
||||
clocks = <&clock CLK_I2C2>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_bus>;
|
||||
|
|
@ -290,7 +292,7 @@
|
|||
interrupts = <0 59 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 297>;
|
||||
clocks = <&clock CLK_I2C3>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_bus>;
|
||||
|
|
@ -303,7 +305,7 @@
|
|||
interrupts = <0 60 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 298>;
|
||||
clocks = <&clock CLK_I2C4>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_bus>;
|
||||
|
|
@ -316,7 +318,7 @@
|
|||
interrupts = <0 61 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 299>;
|
||||
clocks = <&clock CLK_I2C5>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c5_bus>;
|
||||
|
|
@ -329,7 +331,7 @@
|
|||
interrupts = <0 62 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 300>;
|
||||
clocks = <&clock CLK_I2C6>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c6_bus>;
|
||||
|
|
@ -342,7 +344,7 @@
|
|||
interrupts = <0 63 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 301>;
|
||||
clocks = <&clock CLK_I2C7>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c7_bus>;
|
||||
|
|
@ -355,7 +357,7 @@
|
|||
interrupts = <0 64 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 302>;
|
||||
clocks = <&clock CLK_I2C_HDMI>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -365,7 +367,7 @@
|
|||
reg = <0x121D0000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 288>;
|
||||
clocks = <&clock CLK_SATA_PHYI2C>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -380,7 +382,7 @@
|
|||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 304>, <&clock 154>;
|
||||
clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_bus>;
|
||||
|
|
@ -396,7 +398,7 @@
|
|||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 305>, <&clock 155>;
|
||||
clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_bus>;
|
||||
|
|
@ -412,7 +414,7 @@
|
|||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 306>, <&clock 156>;
|
||||
clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_bus>;
|
||||
|
|
@ -424,7 +426,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x12200000 0x1000>;
|
||||
clocks = <&clock 280>, <&clock 139>;
|
||||
clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
|
||||
clock-names = "biu", "ciu";
|
||||
fifo-depth = <0x80>;
|
||||
status = "disabled";
|
||||
|
|
@ -436,7 +438,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x12210000 0x1000>;
|
||||
clocks = <&clock 281>, <&clock 140>;
|
||||
clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
|
||||
clock-names = "biu", "ciu";
|
||||
fifo-depth = <0x80>;
|
||||
status = "disabled";
|
||||
|
|
@ -448,7 +450,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x12220000 0x1000>;
|
||||
clocks = <&clock 282>, <&clock 141>;
|
||||
clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
|
||||
clock-names = "biu", "ciu";
|
||||
fifo-depth = <0x80>;
|
||||
status = "disabled";
|
||||
|
|
@ -460,7 +462,7 @@
|
|||
interrupts = <0 78 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 283>, <&clock 142>;
|
||||
clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
|
||||
clock-names = "biu", "ciu";
|
||||
fifo-depth = <0x80>;
|
||||
status = "disabled";
|
||||
|
|
@ -490,7 +492,7 @@
|
|||
dmas = <&pdma1 12
|
||||
&pdma1 11>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&clock 307>, <&clock 157>;
|
||||
clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
|
||||
clock-names = "iis", "i2s_opclk0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s1_bus>;
|
||||
|
|
@ -503,7 +505,7 @@
|
|||
dmas = <&pdma0 12
|
||||
&pdma0 11>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&clock 308>, <&clock 158>;
|
||||
clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
|
||||
clock-names = "iis", "i2s_opclk0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s2_bus>;
|
||||
|
|
@ -511,7 +513,7 @@
|
|||
|
||||
usb@12000000 {
|
||||
compatible = "samsung,exynos5250-dwusb3";
|
||||
clocks = <&clock 286>;
|
||||
clocks = <&clock CLK_USB3>;
|
||||
clock-names = "usbdrd30";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -528,7 +530,7 @@
|
|||
usb3_phy: usbphy@12100000 {
|
||||
compatible = "samsung,exynos5250-usb3phy";
|
||||
reg = <0x12100000 0x100>;
|
||||
clocks = <&clock 1>, <&clock 286>;
|
||||
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB3>;
|
||||
clock-names = "ext_xtal", "usbdrd30";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -544,7 +546,7 @@
|
|||
reg = <0x12110000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
|
||||
clocks = <&clock 285>;
|
||||
clocks = <&clock CLK_USB2>;
|
||||
clock-names = "usbhost";
|
||||
};
|
||||
|
||||
|
|
@ -553,14 +555,14 @@
|
|||
reg = <0x12120000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
|
||||
clocks = <&clock 285>;
|
||||
clocks = <&clock CLK_USB2>;
|
||||
clock-names = "usbhost";
|
||||
};
|
||||
|
||||
usb2_phy: usbphy@12130000 {
|
||||
compatible = "samsung,exynos5250-usb2phy";
|
||||
reg = <0x12130000 0x100>;
|
||||
clocks = <&clock 1>, <&clock 285>;
|
||||
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>;
|
||||
clock-names = "ext_xtal", "usbhost";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -577,7 +579,7 @@
|
|||
reg = <0x12dd0000 0x100>;
|
||||
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
|
||||
#pwm-cells = <3>;
|
||||
clocks = <&clock 311>;
|
||||
clocks = <&clock CLK_PWM>;
|
||||
clock-names = "timers";
|
||||
};
|
||||
|
||||
|
|
@ -592,7 +594,7 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121A0000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
clocks = <&clock 275>;
|
||||
clocks = <&clock CLK_PDMA0>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
|
|
@ -603,7 +605,7 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121B0000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
clocks = <&clock 276>;
|
||||
clocks = <&clock CLK_PDMA1>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
|
|
@ -614,7 +616,7 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x10800000 0x1000>;
|
||||
interrupts = <0 33 0>;
|
||||
clocks = <&clock 346>;
|
||||
clocks = <&clock CLK_MDMA0>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
|
|
@ -625,7 +627,7 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x11C10000 0x1000>;
|
||||
interrupts = <0 124 0>;
|
||||
clocks = <&clock 271>;
|
||||
clocks = <&clock CLK_MDMA1>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
|
|
@ -638,7 +640,7 @@
|
|||
reg = <0x13e00000 0x1000>;
|
||||
interrupts = <0 85 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 256>;
|
||||
clocks = <&clock CLK_GSCL0>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
|
|
@ -647,7 +649,7 @@
|
|||
reg = <0x13e10000 0x1000>;
|
||||
interrupts = <0 86 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 257>;
|
||||
clocks = <&clock CLK_GSCL1>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
|
|
@ -656,7 +658,7 @@
|
|||
reg = <0x13e20000 0x1000>;
|
||||
interrupts = <0 87 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 258>;
|
||||
clocks = <&clock CLK_GSCL2>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
|
|
@ -665,7 +667,7 @@
|
|||
reg = <0x13e30000 0x1000>;
|
||||
interrupts = <0 88 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 259>;
|
||||
clocks = <&clock CLK_GSCL3>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
|
|
@ -673,8 +675,9 @@
|
|||
compatible = "samsung,exynos4212-hdmi";
|
||||
reg = <0x14530000 0x70000>;
|
||||
interrupts = <0 95 0>;
|
||||
clocks = <&clock 344>, <&clock 136>, <&clock 137>,
|
||||
<&clock 159>, <&clock 1024>;
|
||||
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
|
||||
<&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
|
||||
<&clock CLK_MOUT_HDMI>;
|
||||
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
|
||||
"sclk_hdmiphy", "mout_hdmi";
|
||||
};
|
||||
|
|
@ -683,7 +686,7 @@
|
|||
compatible = "samsung,exynos5250-mixer";
|
||||
reg = <0x14450000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
clocks = <&clock 343>, <&clock 136>;
|
||||
clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
|
||||
clock-names = "mixer", "sclk_hdmi";
|
||||
};
|
||||
|
||||
|
|
@ -694,14 +697,14 @@
|
|||
};
|
||||
|
||||
dp-controller@145B0000 {
|
||||
clocks = <&clock 342>;
|
||||
clocks = <&clock CLK_DP>;
|
||||
clock-names = "dp";
|
||||
phys = <&dp_phy>;
|
||||
phy-names = "dp";
|
||||
};
|
||||
|
||||
fimd@14400000 {
|
||||
clocks = <&clock 133>, <&clock 339>;
|
||||
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
|
||||
clock-names = "sclk_fimd", "fimd";
|
||||
};
|
||||
|
||||
|
|
@ -709,7 +712,7 @@
|
|||
compatible = "samsung,exynos-adc-v1";
|
||||
reg = <0x12D10000 0x100>, <0x10040718 0x4>;
|
||||
interrupts = <0 106 0>;
|
||||
clocks = <&clock 303>;
|
||||
clocks = <&clock CLK_ADC>;
|
||||
clock-names = "adc";
|
||||
#io-channel-cells = <1>;
|
||||
io-channel-ranges;
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/exynos5420.h>
|
||||
#include "exynos5.dtsi"
|
||||
#include "exynos5420-pinctrl.dtsi"
|
||||
|
||||
|
|
@ -119,7 +120,8 @@
|
|||
compatible = "samsung,exynos5420-audss-clock";
|
||||
reg = <0x03810000 0x0C>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>;
|
||||
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
|
||||
<&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
|
||||
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
|
||||
};
|
||||
|
||||
|
|
@ -127,7 +129,7 @@
|
|||
compatible = "samsung,mfc-v7";
|
||||
reg = <0x11000000 0x10000>;
|
||||
interrupts = <0 96 0>;
|
||||
clocks = <&clock 401>;
|
||||
clocks = <&clock CLK_MFC>;
|
||||
clock-names = "mfc";
|
||||
};
|
||||
|
||||
|
|
@ -137,7 +139,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x12200000 0x2000>;
|
||||
clocks = <&clock 351>, <&clock 132>;
|
||||
clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
|
||||
clock-names = "biu", "ciu";
|
||||
fifo-depth = <0x40>;
|
||||
status = "disabled";
|
||||
|
|
@ -149,7 +151,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x12210000 0x2000>;
|
||||
clocks = <&clock 352>, <&clock 133>;
|
||||
clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
|
||||
clock-names = "biu", "ciu";
|
||||
fifo-depth = <0x40>;
|
||||
status = "disabled";
|
||||
|
|
@ -161,7 +163,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x12220000 0x1000>;
|
||||
clocks = <&clock 353>, <&clock 134>;
|
||||
clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
|
||||
clock-names = "biu", "ciu";
|
||||
fifo-depth = <0x40>;
|
||||
status = "disabled";
|
||||
|
|
@ -175,7 +177,7 @@
|
|||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
|
||||
<8>, <9>, <10>, <11>;
|
||||
clocks = <&clock 1>, <&clock 315>;
|
||||
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
|
||||
mct_map: mct-map {
|
||||
|
|
@ -269,7 +271,7 @@
|
|||
};
|
||||
|
||||
rtc@101E0000 {
|
||||
clocks = <&clock 317>;
|
||||
clocks = <&clock CLK_RTC>;
|
||||
clock-names = "rtc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -296,7 +298,7 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121A0000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
clocks = <&clock 362>;
|
||||
clocks = <&clock CLK_PDMA0>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
|
|
@ -307,7 +309,7 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121B0000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
clocks = <&clock 363>;
|
||||
clocks = <&clock CLK_PDMA1>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
|
|
@ -318,7 +320,7 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x10800000 0x1000>;
|
||||
interrupts = <0 33 0>;
|
||||
clocks = <&clock 473>;
|
||||
clocks = <&clock CLK_MDMA0>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
|
|
@ -329,7 +331,7 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x11C10000 0x1000>;
|
||||
interrupts = <0 124 0>;
|
||||
clocks = <&clock 442>;
|
||||
clocks = <&clock CLK_MDMA1>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
|
|
@ -360,7 +362,7 @@
|
|||
dmas = <&pdma1 12
|
||||
&pdma1 11>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&clock 275>, <&clock 138>;
|
||||
clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
|
||||
clock-names = "iis", "i2s_opclk0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s1_bus>;
|
||||
|
|
@ -373,7 +375,7 @@
|
|||
dmas = <&pdma0 12
|
||||
&pdma0 11>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&clock 276>, <&clock 139>;
|
||||
clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
|
||||
clock-names = "iis", "i2s_opclk0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s2_bus>;
|
||||
|
|
@ -391,7 +393,7 @@
|
|||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_bus>;
|
||||
clocks = <&clock 271>, <&clock 135>;
|
||||
clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -407,7 +409,7 @@
|
|||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_bus>;
|
||||
clocks = <&clock 272>, <&clock 136>;
|
||||
clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -423,28 +425,28 @@
|
|||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_bus>;
|
||||
clocks = <&clock 273>, <&clock 137>;
|
||||
clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@12C00000 {
|
||||
clocks = <&clock 257>, <&clock 128>;
|
||||
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C10000 {
|
||||
clocks = <&clock 258>, <&clock 129>;
|
||||
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C20000 {
|
||||
clocks = <&clock 259>, <&clock 130>;
|
||||
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C30000 {
|
||||
clocks = <&clock 260>, <&clock 131>;
|
||||
clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
|
|
@ -453,7 +455,7 @@
|
|||
reg = <0x12dd0000 0x100>;
|
||||
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
|
||||
#pwm-cells = <3>;
|
||||
clocks = <&clock 279>;
|
||||
clocks = <&clock CLK_PWM>;
|
||||
clock-names = "timers";
|
||||
};
|
||||
|
||||
|
|
@ -464,7 +466,7 @@
|
|||
};
|
||||
|
||||
dp-controller@145B0000 {
|
||||
clocks = <&clock 412>;
|
||||
clocks = <&clock CLK_DP1>;
|
||||
clock-names = "dp";
|
||||
phys = <&dp_phy>;
|
||||
phy-names = "dp";
|
||||
|
|
@ -472,7 +474,7 @@
|
|||
|
||||
fimd@14400000 {
|
||||
samsung,power-domain = <&disp_pd>;
|
||||
clocks = <&clock 147>, <&clock 421>;
|
||||
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
|
||||
clock-names = "sclk_fimd", "fimd";
|
||||
};
|
||||
|
||||
|
|
@ -480,7 +482,7 @@
|
|||
compatible = "samsung,exynos-adc-v2";
|
||||
reg = <0x12D10000 0x100>, <0x10040720 0x4>;
|
||||
interrupts = <0 106 0>;
|
||||
clocks = <&clock 270>;
|
||||
clocks = <&clock CLK_TSADC>;
|
||||
clock-names = "adc";
|
||||
#io-channel-cells = <1>;
|
||||
io-channel-ranges;
|
||||
|
|
@ -493,7 +495,7 @@
|
|||
interrupts = <0 56 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 261>;
|
||||
clocks = <&clock CLK_I2C0>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_bus>;
|
||||
|
|
@ -506,7 +508,7 @@
|
|||
interrupts = <0 57 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 262>;
|
||||
clocks = <&clock CLK_I2C1>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_bus>;
|
||||
|
|
@ -519,7 +521,7 @@
|
|||
interrupts = <0 58 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 263>;
|
||||
clocks = <&clock CLK_I2C2>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_bus>;
|
||||
|
|
@ -532,7 +534,7 @@
|
|||
interrupts = <0 59 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 264>;
|
||||
clocks = <&clock CLK_I2C3>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_bus>;
|
||||
|
|
@ -547,7 +549,7 @@
|
|||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_hs_bus>;
|
||||
clocks = <&clock 265>;
|
||||
clocks = <&clock CLK_I2C4>;
|
||||
clock-names = "hsi2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -560,7 +562,7 @@
|
|||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c5_hs_bus>;
|
||||
clocks = <&clock 266>;
|
||||
clocks = <&clock CLK_I2C5>;
|
||||
clock-names = "hsi2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -573,7 +575,7 @@
|
|||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c6_hs_bus>;
|
||||
clocks = <&clock 267>;
|
||||
clocks = <&clock CLK_I2C6>;
|
||||
clock-names = "hsi2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -586,7 +588,7 @@
|
|||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c7_hs_bus>;
|
||||
clocks = <&clock 268>;
|
||||
clocks = <&clock CLK_I2C7>;
|
||||
clock-names = "hsi2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -599,7 +601,7 @@
|
|||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c8_hs_bus>;
|
||||
clocks = <&clock 281>;
|
||||
clocks = <&clock CLK_I2C8>;
|
||||
clock-names = "hsi2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -612,7 +614,7 @@
|
|||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c9_hs_bus>;
|
||||
clocks = <&clock 282>;
|
||||
clocks = <&clock CLK_I2C9>;
|
||||
clock-names = "hsi2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -625,7 +627,7 @@
|
|||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c10_hs_bus>;
|
||||
clocks = <&clock 283>;
|
||||
clocks = <&clock CLK_I2C10>;
|
||||
clock-names = "hsi2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -634,8 +636,9 @@
|
|||
compatible = "samsung,exynos4212-hdmi";
|
||||
reg = <0x14530000 0x70000>;
|
||||
interrupts = <0 95 0>;
|
||||
clocks = <&clock 413>, <&clock 143>, <&clock 768>,
|
||||
<&clock 158>, <&clock 640>;
|
||||
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
|
||||
<&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
|
||||
<&clock CLK_MOUT_HDMI>;
|
||||
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
|
||||
"sclk_hdmiphy", "mout_hdmi";
|
||||
status = "disabled";
|
||||
|
|
@ -645,7 +648,7 @@
|
|||
compatible = "samsung,exynos5420-mixer";
|
||||
reg = <0x14450000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
clocks = <&clock 431>, <&clock 143>;
|
||||
clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
|
||||
clock-names = "mixer", "sclk_hdmi";
|
||||
};
|
||||
|
||||
|
|
@ -653,7 +656,7 @@
|
|||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e00000 0x1000>;
|
||||
interrupts = <0 85 0>;
|
||||
clocks = <&clock 465>;
|
||||
clocks = <&clock CLK_GSCL0>;
|
||||
clock-names = "gscl";
|
||||
samsung,power-domain = <&gsc_pd>;
|
||||
};
|
||||
|
|
@ -662,7 +665,7 @@
|
|||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e10000 0x1000>;
|
||||
interrupts = <0 86 0>;
|
||||
clocks = <&clock 466>;
|
||||
clocks = <&clock CLK_GSCL1>;
|
||||
clock-names = "gscl";
|
||||
samsung,power-domain = <&gsc_pd>;
|
||||
};
|
||||
|
|
@ -676,7 +679,7 @@
|
|||
compatible = "samsung,exynos5420-tmu";
|
||||
reg = <0x10060000 0x100>;
|
||||
interrupts = <0 65 0>;
|
||||
clocks = <&clock 318>;
|
||||
clocks = <&clock CLK_TMU>;
|
||||
clock-names = "tmu_apbif";
|
||||
};
|
||||
|
||||
|
|
@ -684,7 +687,7 @@
|
|||
compatible = "samsung,exynos5420-tmu";
|
||||
reg = <0x10064000 0x100>;
|
||||
interrupts = <0 183 0>;
|
||||
clocks = <&clock 318>;
|
||||
clocks = <&clock CLK_TMU>;
|
||||
clock-names = "tmu_apbif";
|
||||
};
|
||||
|
||||
|
|
@ -692,7 +695,7 @@
|
|||
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
||||
reg = <0x10068000 0x100>, <0x1006c000 0x4>;
|
||||
interrupts = <0 184 0>;
|
||||
clocks = <&clock 318>, <&clock 318>;
|
||||
clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
|
||||
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
||||
};
|
||||
|
||||
|
|
@ -700,7 +703,7 @@
|
|||
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
||||
reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
|
||||
interrupts = <0 185 0>;
|
||||
clocks = <&clock 318>, <&clock 319>;
|
||||
clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
|
||||
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
||||
};
|
||||
|
||||
|
|
@ -708,7 +711,7 @@
|
|||
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
||||
reg = <0x100a0000 0x100>, <0x10068000 0x4>;
|
||||
interrupts = <0 215 0>;
|
||||
clocks = <&clock 319>, <&clock 318>;
|
||||
clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
|
||||
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
||||
};
|
||||
|
||||
|
|
@ -716,7 +719,7 @@
|
|||
compatible = "samsung,exynos5420-wdt";
|
||||
reg = <0x101D0000 0x100>;
|
||||
interrupts = <0 42 0>;
|
||||
clocks = <&clock 316>;
|
||||
clocks = <&clock CLK_WDT>;
|
||||
clock-names = "watchdog";
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/exynos5440.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
@ -105,7 +106,7 @@
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0xB0000 0x1000>;
|
||||
interrupts = <0 2 0>;
|
||||
clocks = <&clock 21>, <&clock 21>;
|
||||
clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
|
|
@ -113,7 +114,7 @@
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0xC0000 0x1000>;
|
||||
interrupts = <0 3 0>;
|
||||
clocks = <&clock 21>, <&clock 21>;
|
||||
clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
|
|
@ -125,7 +126,7 @@
|
|||
#size-cells = <0>;
|
||||
samsung,spi-src-clk = <0>;
|
||||
num-cs = <1>;
|
||||
clocks = <&clock 21>, <&clock 16>;
|
||||
clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
};
|
||||
|
||||
|
|
@ -161,7 +162,7 @@
|
|||
interrupts = <0 5 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 21>;
|
||||
clocks = <&clock CLK_B_125>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
|
|
@ -171,7 +172,7 @@
|
|||
interrupts = <0 6 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 21>;
|
||||
clocks = <&clock CLK_B_125>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
|
|
@ -179,7 +180,7 @@
|
|||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x110000 0x1000>;
|
||||
interrupts = <0 1 0>;
|
||||
clocks = <&clock 21>;
|
||||
clocks = <&clock CLK_B_125>;
|
||||
clock-names = "watchdog";
|
||||
};
|
||||
|
||||
|
|
@ -190,7 +191,7 @@
|
|||
interrupts = <0 31 4>;
|
||||
interrupt-names = "macirq";
|
||||
phy-mode = "sgmii";
|
||||
clocks = <&clock 25>;
|
||||
clocks = <&clock CLK_GMAC0>;
|
||||
clock-names = "stmmaceth";
|
||||
};
|
||||
|
||||
|
|
@ -206,7 +207,7 @@
|
|||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x130000 0x1000>;
|
||||
interrupts = <0 17 0>, <0 16 0>;
|
||||
clocks = <&clock 21>;
|
||||
clocks = <&clock CLK_B_125>;
|
||||
clock-names = "rtc";
|
||||
};
|
||||
|
||||
|
|
@ -214,7 +215,7 @@
|
|||
compatible = "samsung,exynos5440-tmu";
|
||||
reg = <0x160118 0x230>, <0x160368 0x10>;
|
||||
interrupts = <0 58 0>;
|
||||
clocks = <&clock 21>;
|
||||
clocks = <&clock CLK_B_125>;
|
||||
clock-names = "tmu_apbif";
|
||||
};
|
||||
|
||||
|
|
@ -222,7 +223,7 @@
|
|||
compatible = "samsung,exynos5440-tmu";
|
||||
reg = <0x16011C 0x230>, <0x160368 0x10>;
|
||||
interrupts = <0 58 0>;
|
||||
clocks = <&clock 21>;
|
||||
clocks = <&clock CLK_B_125>;
|
||||
clock-names = "tmu_apbif";
|
||||
};
|
||||
|
||||
|
|
@ -230,7 +231,7 @@
|
|||
compatible = "samsung,exynos5440-tmu";
|
||||
reg = <0x160120 0x230>, <0x160368 0x10>;
|
||||
interrupts = <0 58 0>;
|
||||
clocks = <&clock 21>;
|
||||
clocks = <&clock CLK_B_125>;
|
||||
clock-names = "tmu_apbif";
|
||||
};
|
||||
|
||||
|
|
@ -238,7 +239,7 @@
|
|||
compatible = "snps,exynos5440-ahci";
|
||||
reg = <0x210000 0x10000>;
|
||||
interrupts = <0 30 0>;
|
||||
clocks = <&clock 23>;
|
||||
clocks = <&clock CLK_SATA>;
|
||||
clock-names = "sata";
|
||||
};
|
||||
|
||||
|
|
@ -246,7 +247,7 @@
|
|||
compatible = "samsung,exynos5440-ohci";
|
||||
reg = <0x220000 0x1000>;
|
||||
interrupts = <0 29 0>;
|
||||
clocks = <&clock 24>;
|
||||
clocks = <&clock CLK_USB>;
|
||||
clock-names = "usbhost";
|
||||
};
|
||||
|
||||
|
|
@ -254,7 +255,7 @@
|
|||
compatible = "samsung,exynos5440-ehci";
|
||||
reg = <0x221000 0x1000>;
|
||||
interrupts = <0 29 0>;
|
||||
clocks = <&clock 24>;
|
||||
clocks = <&clock CLK_USB>;
|
||||
clock-names = "usbhost";
|
||||
};
|
||||
|
||||
|
|
@ -264,7 +265,7 @@
|
|||
0x270000 0x1000
|
||||
0x271000 0x40>;
|
||||
interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
|
||||
clocks = <&clock 28>, <&clock 27>;
|
||||
clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -285,7 +286,7 @@
|
|||
0x272000 0x1000
|
||||
0x271040 0x40>;
|
||||
interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
|
||||
clocks = <&clock 29>, <&clock 27>;
|
||||
clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue