PM / devfreq: exynos4: use common PPMU code
This patch converts exynos4_bus driver to use common PPMU code (exynos_ppmu.c) instead of individual functions related to PPC because PPMU is integrated module with both PPC and Bus event generator. When using PPMU to get bus performance read/write event exynos4_bus driver deson't need to consider memory type. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> [bzolnier: splitted out changes from the bigger patch] Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
This commit is contained in:
Chanwoo Choi
MyungJoo Ham
parent
ae29fa1d50
commit
ba778b374d
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@ -1,3 +1,3 @@
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# Exynos DEVFREQ Drivers
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obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos4_bus.o
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obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos_ppmu.o exynos4_bus.o
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obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos_ppmu.o exynos5_bus.o
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@ -25,15 +25,16 @@
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#include <linux/regulator/consumer.h>
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#include <linux/module.h>
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#include <mach/map.h>
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#include "exynos_ppmu.h"
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#include "exynos4_bus.h"
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/* Exynos4 ASV has been in the mailing list, but not upstreamed, yet. */
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#ifdef CONFIG_EXYNOS_ASV
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extern unsigned int exynos_result_of_asv;
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#endif
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#include <mach/map.h>
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#include "exynos4_bus.h"
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#define MAX_SAFEVOLT 1200000 /* 1.2V */
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enum exynos4_busf_type {
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@ -44,22 +45,6 @@ enum exynos4_busf_type {
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/* Assume that the bus is saturated if the utilization is 40% */
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#define BUS_SATURATION_RATIO 40
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enum ppmu_counter {
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PPMU_PMNCNT0 = 0,
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PPMU_PMCCNT1,
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PPMU_PMNCNT2,
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PPMU_PMNCNT3,
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PPMU_PMNCNT_MAX,
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};
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struct exynos4_ppmu {
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void __iomem *hw_base;
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unsigned int ccnt;
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unsigned int event;
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unsigned int count[PPMU_PMNCNT_MAX];
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bool ccnt_overflow;
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bool count_overflow[PPMU_PMNCNT_MAX];
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};
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enum busclk_level_idx {
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LV_0 = 0,
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LV_1,
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@ -68,6 +53,13 @@ enum busclk_level_idx {
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LV_4,
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_LV_END
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};
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enum exynos_ppmu_idx {
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PPMU_DMC0,
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PPMU_DMC1,
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PPMU_END,
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};
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#define EX4210_LV_MAX LV_2
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#define EX4x12_LV_MAX LV_4
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#define EX4210_LV_NUM (LV_2 + 1)
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@ -91,7 +83,7 @@ struct busfreq_data {
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struct regulator *vdd_int;
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struct regulator *vdd_mif; /* Exynos4412/4212 only */
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struct busfreq_opp_info curr_oppinfo;
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struct exynos4_ppmu dmc[2];
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struct exynos_ppmu ppmu[PPMU_END];
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struct notifier_block pm_notifier;
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struct mutex lock;
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@ -101,12 +93,6 @@ struct busfreq_data {
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unsigned int top_divtable[_LV_END];
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};
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struct bus_opp_table {
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unsigned int idx;
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unsigned long clk;
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unsigned long volt;
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};
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/* 4210 controls clock of mif and voltage of int */
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static struct bus_opp_table exynos4210_busclk_table[] = {
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{LV_0, 400000, 1150000},
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@ -524,27 +510,22 @@ static int exynos4x12_set_busclk(struct busfreq_data *data,
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return 0;
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}
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static void busfreq_mon_reset(struct busfreq_data *data)
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{
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unsigned int i;
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for (i = 0; i < 2; i++) {
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void __iomem *ppmu_base = data->dmc[i].hw_base;
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for (i = 0; i < PPMU_END; i++) {
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void __iomem *ppmu_base = data->ppmu[i].hw_base;
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/* Reset PPMU */
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__raw_writel(0x8000000f, ppmu_base + 0xf010);
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__raw_writel(0x8000000f, ppmu_base + 0xf050);
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__raw_writel(0x6, ppmu_base + 0xf000);
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__raw_writel(0x0, ppmu_base + 0xf100);
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/* Reset the performance and cycle counters */
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exynos_ppmu_reset(ppmu_base);
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/* Set PPMU Event */
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data->dmc[i].event = 0x6;
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__raw_writel(((data->dmc[i].event << 12) | 0x1),
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ppmu_base + 0xfc);
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/* Setup count registers to monitor read/write transactions */
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data->ppmu[i].event[PPMU_PMNCNT3] = RDWR_DATA_COUNT;
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exynos_ppmu_setevent(ppmu_base, PPMU_PMNCNT3,
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data->ppmu[i].event[PPMU_PMNCNT3]);
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/* Start PPMU */
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__raw_writel(0x1, ppmu_base + 0xf000);
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exynos_ppmu_start(ppmu_base);
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}
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}
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@ -552,23 +533,20 @@ static void exynos4_read_ppmu(struct busfreq_data *data)
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{
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int i, j;
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for (i = 0; i < 2; i++) {
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void __iomem *ppmu_base = data->dmc[i].hw_base;
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u32 overflow;
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for (i = 0; i < PPMU_END; i++) {
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void __iomem *ppmu_base = data->ppmu[i].hw_base;
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/* Stop PPMU */
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__raw_writel(0x0, ppmu_base + 0xf000);
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exynos_ppmu_stop(ppmu_base);
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/* Update local data from PPMU */
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overflow = __raw_readl(ppmu_base + 0xf050);
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data->ppmu[i].ccnt = __raw_readl(ppmu_base + PPMU_CCNT);
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data->dmc[i].ccnt = __raw_readl(ppmu_base + 0xf100);
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data->dmc[i].ccnt_overflow = overflow & (1 << 31);
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for (j = 0; j < PPMU_PMNCNT_MAX; j++) {
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data->dmc[i].count[j] = __raw_readl(
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ppmu_base + (0xf110 + (0x10 * j)));
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data->dmc[i].count_overflow[j] = overflow & (1 << j);
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for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) {
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if (data->ppmu[i].event[j] == 0)
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data->ppmu[i].count[j] = 0;
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else
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data->ppmu[i].count[j] =
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exynos_ppmu_read(ppmu_base, j);
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}
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}
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@ -698,66 +676,42 @@ out:
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return err;
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}
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static int exynos4_get_busier_dmc(struct busfreq_data *data)
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static int exynos4_get_busier_ppmu(struct busfreq_data *data)
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{
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u64 p0 = data->dmc[0].count[0];
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u64 p1 = data->dmc[1].count[0];
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int i, j;
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int busy = 0;
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unsigned int temp = 0;
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p0 *= data->dmc[1].ccnt;
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p1 *= data->dmc[0].ccnt;
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for (i = 0; i < PPMU_END; i++) {
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for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) {
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if (data->ppmu[i].count[j] > temp) {
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temp = data->ppmu[i].count[j];
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busy = i;
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}
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}
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}
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if (data->dmc[1].ccnt == 0)
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return 0;
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if (p0 > p1)
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return 0;
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return 1;
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return busy;
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}
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static int exynos4_bus_get_dev_status(struct device *dev,
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struct devfreq_dev_status *stat)
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{
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struct busfreq_data *data = dev_get_drvdata(dev);
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int busier_dmc;
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int cycles_x2 = 2; /* 2 x cycles */
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void __iomem *addr;
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u32 timing;
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u32 memctrl;
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int busier;
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exynos4_read_ppmu(data);
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busier_dmc = exynos4_get_busier_dmc(data);
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busier = exynos4_get_busier_ppmu(data);
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stat->current_frequency = data->curr_oppinfo.rate;
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if (busier_dmc)
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addr = S5P_VA_DMC1;
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else
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addr = S5P_VA_DMC0;
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memctrl = __raw_readl(addr + 0x04); /* one of DDR2/3/LPDDR2 */
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timing = __raw_readl(addr + 0x38); /* CL or WL/RL values */
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switch ((memctrl >> 8) & 0xf) {
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case 0x4: /* DDR2 */
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cycles_x2 = ((timing >> 16) & 0xf) * 2;
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break;
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case 0x5: /* LPDDR2 */
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case 0x6: /* DDR3 */
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cycles_x2 = ((timing >> 8) & 0xf) + ((timing >> 0) & 0xf);
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break;
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default:
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pr_err("%s: Unknown Memory Type(%d).\n", __func__,
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(memctrl >> 8) & 0xf);
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return -EINVAL;
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}
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/* Number of cycles spent on memory access */
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stat->busy_time = data->dmc[busier_dmc].count[0] / 2 * (cycles_x2 + 2);
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stat->busy_time = data->ppmu[busier].count[PPMU_PMNCNT3];
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stat->busy_time *= 100 / BUS_SATURATION_RATIO;
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stat->total_time = data->dmc[busier_dmc].ccnt;
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stat->total_time = data->ppmu[busier].ccnt;
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/* If the counters have overflown, retry */
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if (data->dmc[busier_dmc].ccnt_overflow ||
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data->dmc[busier_dmc].count_overflow[0])
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if (data->ppmu[busier].ccnt_overflow ||
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data->ppmu[busier].count_overflow[0])
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return -EAGAIN;
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return 0;
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@ -1023,8 +977,8 @@ static int exynos4_busfreq_probe(struct platform_device *pdev)
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}
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data->type = pdev->id_entry->driver_data;
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data->dmc[0].hw_base = S5P_VA_DMC0;
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data->dmc[1].hw_base = S5P_VA_DMC1;
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data->ppmu[PPMU_DMC0].hw_base = S5P_VA_DMC0;
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data->ppmu[PPMU_DMC1].hw_base = S5P_VA_DMC1;
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data->pm_notifier.notifier_call = exynos4_busfreq_pm_notifier_event;
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data->dev = dev;
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mutex_init(&data->lock);
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@ -1074,13 +1028,17 @@ static int exynos4_busfreq_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, data);
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busfreq_mon_reset(data);
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data->devfreq = devfreq_add_device(dev, &exynos4_devfreq_profile,
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"simple_ondemand", NULL);
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if (IS_ERR(data->devfreq))
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return PTR_ERR(data->devfreq);
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/*
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* Start PPMU (Performance Profiling Monitoring Unit) to check
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* utilization of each IP in the Exynos4 SoC.
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*/
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busfreq_mon_reset(data);
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/* Register opp_notifier for Exynos4 busfreq */
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err = devfreq_register_opp_notifier(dev, data->devfreq);
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if (err < 0) {
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