perf/x86: Use the new pmu::update_attrs attribute group
Using the new pmu::update_attrs attribute group to create detected events for x86_pmu. Moving the topdown/memory/tsx attributes to separate attribute groups with specific is_visible functions. Signed-off-by: Jiri Olsa <jolsa@kernel.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20190512155518.21468-5-jolsa@kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
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21b0dbc5e8
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@ -1855,14 +1855,6 @@ static int __init init_hw_perf_events(void)
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else
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filter_events(x86_pmu_events_group.attrs);
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if (x86_pmu.cpu_events) {
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struct attribute **tmp;
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tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
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if (!WARN_ON(!tmp))
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x86_pmu_events_group.attrs = tmp;
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}
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if (x86_pmu.attrs) {
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struct attribute **tmp;
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@ -1871,6 +1863,8 @@ static int __init init_hw_perf_events(void)
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x86_pmu_attr_group.attrs = tmp;
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}
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pmu.attr_update = x86_pmu.attr_update;
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pr_info("... version: %d\n", x86_pmu.version);
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pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
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pr_info("... generic registers: %d\n", x86_pmu.num_counters);
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@ -4274,13 +4274,6 @@ static struct attribute *icl_tsx_events_attrs[] = {
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NULL,
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};
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static __init struct attribute **get_icl_events_attrs(void)
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{
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return boot_cpu_has(X86_FEATURE_RTM) ?
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merge_attr(icl_events_attrs, icl_tsx_events_attrs) :
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icl_events_attrs;
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}
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static ssize_t freeze_on_smi_show(struct device *cdev,
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struct device_attribute *attr,
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char *buf)
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@ -4406,32 +4399,47 @@ static struct attribute *intel_pmu_attrs[] = {
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NULL,
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};
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static __init struct attribute **
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get_events_attrs(struct attribute **base,
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struct attribute **mem,
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struct attribute **tsx)
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static umode_t
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tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
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{
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struct attribute **attrs = base;
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struct attribute **old;
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if (mem && x86_pmu.pebs)
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attrs = merge_attr(attrs, mem);
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if (tsx && boot_cpu_has(X86_FEATURE_RTM)) {
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old = attrs;
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attrs = merge_attr(attrs, tsx);
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if (old != base)
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kfree(old);
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}
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return attrs;
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return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
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}
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static umode_t
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pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
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{
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return x86_pmu.pebs ? attr->mode : 0;
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}
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static struct attribute_group group_events_td = {
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.name = "events",
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};
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static struct attribute_group group_events_mem = {
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.name = "events",
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.is_visible = pebs_is_visible,
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};
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static struct attribute_group group_events_tsx = {
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.name = "events",
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.is_visible = tsx_is_visible,
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};
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static const struct attribute_group *attr_update[] = {
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&group_events_td,
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&group_events_mem,
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&group_events_tsx,
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NULL,
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};
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static struct attribute *empty_attrs;
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__init int intel_pmu_init(void)
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{
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struct attribute **extra_attr = NULL;
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struct attribute **mem_attr = NULL;
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struct attribute **tsx_attr = NULL;
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struct attribute **extra_attr = &empty_attrs;
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struct attribute **td_attr = &empty_attrs;
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struct attribute **mem_attr = &empty_attrs;
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struct attribute **tsx_attr = &empty_attrs;
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struct attribute **to_free = NULL;
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union cpuid10_edx edx;
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union cpuid10_eax eax;
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@ -4596,7 +4604,7 @@ __init int intel_pmu_init(void)
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x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
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x86_pmu.extra_regs = intel_slm_extra_regs;
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x86_pmu.flags |= PMU_FL_HAS_RSP_1;
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x86_pmu.cpu_events = slm_events_attrs;
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td_attr = slm_events_attrs;
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extra_attr = slm_format_attr;
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pr_cont("Silvermont events, ");
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name = "silvermont";
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@ -4624,7 +4632,7 @@ __init int intel_pmu_init(void)
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x86_pmu.pebs_prec_dist = true;
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x86_pmu.lbr_pt_coexist = true;
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x86_pmu.flags |= PMU_FL_HAS_RSP_1;
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x86_pmu.cpu_events = glm_events_attrs;
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td_attr = glm_events_attrs;
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extra_attr = slm_format_attr;
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pr_cont("Goldmont events, ");
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name = "goldmont";
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@ -4651,7 +4659,7 @@ __init int intel_pmu_init(void)
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x86_pmu.flags |= PMU_FL_HAS_RSP_1;
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x86_pmu.flags |= PMU_FL_PEBS_ALL;
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x86_pmu.get_event_constraints = glp_get_event_constraints;
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x86_pmu.cpu_events = glm_events_attrs;
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td_attr = glm_events_attrs;
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/* Goldmont Plus has 4-wide pipeline */
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event_attr_td_total_slots_scale_glm.event_str = "4";
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extra_attr = slm_format_attr;
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@ -4740,7 +4748,7 @@ __init int intel_pmu_init(void)
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x86_pmu.flags |= PMU_FL_HAS_RSP_1;
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x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
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x86_pmu.cpu_events = snb_events_attrs;
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td_attr = snb_events_attrs;
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mem_attr = snb_mem_events_attrs;
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/* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
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@ -4781,7 +4789,7 @@ __init int intel_pmu_init(void)
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x86_pmu.flags |= PMU_FL_HAS_RSP_1;
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x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
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x86_pmu.cpu_events = snb_events_attrs;
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td_attr = snb_events_attrs;
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mem_attr = snb_mem_events_attrs;
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/* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
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@ -4818,10 +4826,10 @@ __init int intel_pmu_init(void)
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x86_pmu.hw_config = hsw_hw_config;
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x86_pmu.get_event_constraints = hsw_get_event_constraints;
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x86_pmu.cpu_events = hsw_events_attrs;
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x86_pmu.lbr_double_abort = true;
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extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
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hsw_format_attr : nhm_format_attr;
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td_attr = hsw_events_attrs;
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mem_attr = hsw_mem_events_attrs;
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tsx_attr = hsw_tsx_events_attrs;
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pr_cont("Haswell events, ");
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@ -4860,10 +4868,10 @@ __init int intel_pmu_init(void)
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x86_pmu.hw_config = hsw_hw_config;
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x86_pmu.get_event_constraints = hsw_get_event_constraints;
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x86_pmu.cpu_events = hsw_events_attrs;
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x86_pmu.limit_period = bdw_limit_period;
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extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
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hsw_format_attr : nhm_format_attr;
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td_attr = hsw_events_attrs;
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mem_attr = hsw_mem_events_attrs;
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tsx_attr = hsw_tsx_events_attrs;
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pr_cont("Broadwell events, ");
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@ -4922,7 +4930,7 @@ __init int intel_pmu_init(void)
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hsw_format_attr : nhm_format_attr;
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extra_attr = merge_attr(extra_attr, skl_format_attr);
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to_free = extra_attr;
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x86_pmu.cpu_events = hsw_events_attrs;
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td_attr = hsw_events_attrs;
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mem_attr = hsw_mem_events_attrs;
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tsx_attr = hsw_tsx_events_attrs;
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intel_pmu_pebs_data_source_skl(
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@ -4960,7 +4968,8 @@ __init int intel_pmu_init(void)
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extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
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hsw_format_attr : nhm_format_attr;
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extra_attr = merge_attr(extra_attr, skl_format_attr);
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x86_pmu.cpu_events = get_icl_events_attrs();
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mem_attr = icl_events_attrs;
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tsx_attr = icl_tsx_events_attrs;
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x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xca, .umask=0x02);
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x86_pmu.lbr_pt_coexist = true;
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intel_pmu_pebs_data_source_skl(false);
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@ -4994,8 +5003,11 @@ __init int intel_pmu_init(void)
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WARN_ON(!x86_pmu.format_attrs);
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}
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x86_pmu.cpu_events = get_events_attrs(x86_pmu.cpu_events,
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mem_attr, tsx_attr);
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group_events_td.attrs = td_attr;
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group_events_mem.attrs = mem_attr;
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group_events_tsx.attrs = tsx_attr;
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x86_pmu.attr_update = attr_update;
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if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
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WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
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@ -634,7 +634,7 @@ struct x86_pmu {
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struct attribute **caps_attrs;
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ssize_t (*events_sysfs_show)(char *page, u64 config);
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struct attribute **cpu_events;
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const struct attribute_group **attr_update;
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unsigned long attr_freeze_on_smi;
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struct attribute **attrs;
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