[SPARC64]: More SUN4V PCI controller work.
Add assembler file for PCI hypervisor calls. Setup basic skeleton of SUN4V PCI controller driver. Add 32-bit devhandle to PBM struct, as this is needed for hypervisor calls. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
parent
8f6a93a196
commit
bade562216
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@ -14,7 +14,8 @@ obj-y := process.o setup.o cpu.o idprom.o \
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power.o sbus.o iommu_common.o sparc64_ksyms.o chmc.o
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obj-$(CONFIG_PCI) += ebus.o isa.o pci_common.o pci_iommu.o \
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pci_psycho.o pci_sabre.o pci_schizo.o pci_sun4v.o
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pci_psycho.o pci_sabre.o pci_schizo.o \
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pci_sun4v.o pci_sun4v_asm.o
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obj-$(CONFIG_SMP) += smp.o trampoline.o
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obj-$(CONFIG_SPARC32_COMPAT) += sys32.o sys_sparc32.o signal32.o
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obj-$(CONFIG_BINFMT_ELF32) += binfmt_elf32.o
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@ -21,6 +21,8 @@
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#include "pci_impl.h"
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#include "iommu_common.h"
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#include "pci_sun4v.h"
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static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp)
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{
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return NULL;
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@ -67,8 +69,292 @@ struct pci_iommu_ops pci_sun4v_iommu_ops = {
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.dma_sync_sg_for_cpu = pci_4v_dma_sync_sg_for_cpu,
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};
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/* SUN4V PCI configuration space accessors. */
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static int pci_sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
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int where, int size, u32 *value)
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{
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/* XXX Implement me! XXX */
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return 0;
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}
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static int pci_sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
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int where, int size, u32 value)
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{
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/* XXX Implement me! XXX */
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return 0;
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}
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static struct pci_ops pci_sun4v_ops = {
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.read = pci_sun4v_read_pci_cfg,
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.write = pci_sun4v_write_pci_cfg,
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};
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static void pci_sun4v_scan_bus(struct pci_controller_info *p)
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{
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/* XXX Implement me! XXX */
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}
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static unsigned int pci_sun4v_irq_build(struct pci_pbm_info *pbm,
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struct pci_dev *pdev,
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unsigned int ino)
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{
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/* XXX Implement me! XXX */
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return 0;
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}
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/* XXX correct? XXX */
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static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
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{
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struct pcidev_cookie *pcp = pdev->sysdata;
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struct pci_pbm_info *pbm = pcp->pbm;
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struct resource *res, *root;
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u32 reg;
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int where, size, is_64bit;
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res = &pdev->resource[resource];
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if (resource < 6) {
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where = PCI_BASE_ADDRESS_0 + (resource * 4);
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} else if (resource == PCI_ROM_RESOURCE) {
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where = pdev->rom_base_reg;
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} else {
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/* Somebody might have asked allocation of a non-standard resource */
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return;
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}
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is_64bit = 0;
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if (res->flags & IORESOURCE_IO)
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root = &pbm->io_space;
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else {
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root = &pbm->mem_space;
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if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
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== PCI_BASE_ADDRESS_MEM_TYPE_64)
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is_64bit = 1;
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}
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size = res->end - res->start;
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pci_read_config_dword(pdev, where, ®);
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reg = ((reg & size) |
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(((u32)(res->start - root->start)) & ~size));
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if (resource == PCI_ROM_RESOURCE) {
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reg |= PCI_ROM_ADDRESS_ENABLE;
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res->flags |= IORESOURCE_ROM_ENABLE;
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}
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pci_write_config_dword(pdev, where, reg);
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/* This knows that the upper 32-bits of the address
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* must be zero. Our PCI common layer enforces this.
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*/
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if (is_64bit)
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pci_write_config_dword(pdev, where + 4, 0);
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}
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/* XXX correct? XXX */
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static void pci_sun4v_resource_adjust(struct pci_dev *pdev,
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struct resource *res,
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struct resource *root)
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{
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res->start += root->start;
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res->end += root->start;
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}
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/* Use ranges property to determine where PCI MEM, I/O, and Config
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* space are for this PCI bus module.
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*/
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static void pci_sun4v_determine_mem_io_space(struct pci_pbm_info *pbm)
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{
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int i, saw_cfg, saw_mem, saw_io;
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saw_cfg = saw_mem = saw_io = 0;
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for (i = 0; i < pbm->num_pbm_ranges; i++) {
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struct linux_prom_pci_ranges *pr = &pbm->pbm_ranges[i];
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unsigned long a;
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int type;
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type = (pr->child_phys_hi >> 24) & 0x3;
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a = (((unsigned long)pr->parent_phys_hi << 32UL) |
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((unsigned long)pr->parent_phys_lo << 0UL));
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switch (type) {
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case 0:
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/* PCI config space, 16MB */
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pbm->config_space = a;
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saw_cfg = 1;
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break;
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case 1:
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/* 16-bit IO space, 16MB */
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pbm->io_space.start = a;
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pbm->io_space.end = a + ((16UL*1024UL*1024UL) - 1UL);
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pbm->io_space.flags = IORESOURCE_IO;
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saw_io = 1;
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break;
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case 2:
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/* 32-bit MEM space, 2GB */
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pbm->mem_space.start = a;
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pbm->mem_space.end = a + (0x80000000UL - 1UL);
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pbm->mem_space.flags = IORESOURCE_MEM;
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saw_mem = 1;
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break;
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default:
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break;
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};
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}
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if (!saw_cfg || !saw_io || !saw_mem) {
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prom_printf("%s: Fatal error, missing %s PBM range.\n",
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pbm->name,
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((!saw_cfg ?
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"CFG" :
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(!saw_io ?
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"IO" : "MEM"))));
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prom_halt();
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}
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printk("%s: PCI CFG[%lx] IO[%lx] MEM[%lx]\n",
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pbm->name,
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pbm->config_space,
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pbm->io_space.start,
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pbm->mem_space.start);
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}
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static void pbm_register_toplevel_resources(struct pci_controller_info *p,
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struct pci_pbm_info *pbm)
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{
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pbm->io_space.name = pbm->mem_space.name = pbm->name;
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request_resource(&ioport_resource, &pbm->io_space);
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request_resource(&iomem_resource, &pbm->mem_space);
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pci_register_legacy_regions(&pbm->io_space,
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&pbm->mem_space);
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}
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static void pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
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{
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/* XXX Implement me! XXX */
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}
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static void pci_sun4v_pbm_init(struct pci_controller_info *p, int prom_node)
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{
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struct pci_pbm_info *pbm;
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struct linux_prom64_registers regs;
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unsigned int busrange[2];
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int err;
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/* XXX */
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pbm = &p->pbm_A;
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pbm->parent = p;
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pbm->prom_node = prom_node;
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pbm->pci_first_slot = 1;
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prom_getproperty(prom_node, "reg", (char *)®s, sizeof(regs));
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pbm->devhandle = (regs.phys_addr >> 32UL) & 0x0fffffff;
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sprintf(pbm->name, "SUN4V-PCI%d PBM%c",
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p->index, (pbm == &p->pbm_A ? 'A' : 'B'));
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printk("%s: devhandle[%x]\n", pbm->name, pbm->devhandle);
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prom_getstring(prom_node, "name",
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pbm->prom_name, sizeof(pbm->prom_name));
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err = prom_getproperty(prom_node, "ranges",
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(char *) pbm->pbm_ranges,
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sizeof(pbm->pbm_ranges));
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if (err == 0 || err == -1) {
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prom_printf("%s: Fatal error, no ranges property.\n",
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pbm->name);
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prom_halt();
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}
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pbm->num_pbm_ranges =
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(err / sizeof(struct linux_prom_pci_ranges));
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pci_sun4v_determine_mem_io_space(pbm);
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pbm_register_toplevel_resources(p, pbm);
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err = prom_getproperty(prom_node, "interrupt-map",
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(char *)pbm->pbm_intmap,
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sizeof(pbm->pbm_intmap));
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if (err != -1) {
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pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
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err = prom_getproperty(prom_node, "interrupt-map-mask",
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(char *)&pbm->pbm_intmask,
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sizeof(pbm->pbm_intmask));
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if (err == -1) {
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prom_printf("%s: Fatal error, no "
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"interrupt-map-mask.\n", pbm->name);
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prom_halt();
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}
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} else {
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pbm->num_pbm_intmap = 0;
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memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
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}
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err = prom_getproperty(prom_node, "bus-range",
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(char *)&busrange[0],
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sizeof(busrange));
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if (err == 0 || err == -1) {
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prom_printf("%s: Fatal error, no bus-range.\n", pbm->name);
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prom_halt();
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}
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pbm->pci_first_busno = busrange[0];
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pbm->pci_last_busno = busrange[1];
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pci_sun4v_iommu_init(pbm);
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}
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void sun4v_pci_init(int node, char *model_name)
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{
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struct pci_controller_info *p;
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struct pci_iommu *iommu;
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p = kmalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
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if (!p) {
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prom_printf("SUN4V_PCI: Fatal memory allocation error.\n");
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prom_halt();
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}
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memset(p, 0, sizeof(*p));
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iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
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if (!iommu) {
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prom_printf("SCHIZO: Fatal memory allocation error.\n");
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prom_halt();
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}
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memset(iommu, 0, sizeof(*iommu));
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p->pbm_A.iommu = iommu;
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iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
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if (!iommu) {
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prom_printf("SCHIZO: Fatal memory allocation error.\n");
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prom_halt();
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}
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memset(iommu, 0, sizeof(*iommu));
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p->pbm_B.iommu = iommu;
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p->next = pci_controller_root;
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pci_controller_root = p;
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p->index = pci_num_controllers++;
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p->pbms_same_domain = 0;
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p->scan_bus = pci_sun4v_scan_bus;
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p->irq_build = pci_sun4v_irq_build;
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p->base_address_update = pci_sun4v_base_address_update;
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p->resource_adjust = pci_sun4v_resource_adjust;
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p->pci_ops = &pci_sun4v_ops;
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/* Like PSYCHO and SCHIZO we have a 2GB aligned area
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* for memory space.
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*/
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pci_memspace_mask = 0x7fffffffUL;
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pci_sun4v_pbm_init(p, node);
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prom_printf("sun4v_pci_init: Implement me.\n");
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prom_halt();
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}
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@ -0,0 +1,20 @@
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/* pci_sun4v.h: SUN4V specific PCI controller support.
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*
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* Copyright (C) 2006 David S. Miller (davem@davemloft.net)
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*/
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#ifndef _PCI_SUN4V_H
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#define _PCI_SUN4V_H
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extern unsigned long pci_sun4v_devino_to_sysino(unsigned long devhandle,
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unsigned long deino);
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extern unsigned long pci_sun4v_iommu_map(unsigned long devhandle,
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unsigned long tsbid,
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unsigned long num_ttes,
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unsigned long io_attributes,
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unsigned long io_page_list_pa);
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extern unsigned long pci_sun4v_iommu_demap(unsigned long devhandle,
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unsigned long tsbid,
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unsigned long num_ttes);
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#endif /* !(_PCI_SUN4V_H) */
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@ -0,0 +1,56 @@
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/* pci_sun4v_asm: Hypervisor calls for PCI support.
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*
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* Copyright (C) 2006 David S. Miller <davem@davemloft.net>
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*/
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#include <asm/hypervisor.h>
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/* %o0: devhandle
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* %o1: devino
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*
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* returns %o0: sysino
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*/
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.globl pci_sun4v_devino_to_sysino
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pci_sun4v_devino_to_sysino:
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mov %o1, %o2
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mov %o0, %o1
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mov HV_FAST_INTR_DEVINO2SYSINO, %o0
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ta HV_FAST_TRAP
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retl
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mov %o1, %o0
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/* %o0: devhandle
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* %o1: tsbid
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* %o2: num ttes
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* %o3: io_attributes
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* %o4: io_page_list phys address
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*
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* returns %o0: num ttes mapped
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*/
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.globl pci_sun4v_iommu_map
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pci_sun4v_iommu_map:
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mov %o4, %o5
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mov %o3, %o4
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mov %o2, %o3
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mov %o1, %o2
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mov %o0, %o1
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mov HV_FAST_PCI_IOMMU_MAP, %o0
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ta HV_FAST_TRAP
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retl
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mov %o1, %o0
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/* %o0: devhandle
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* %o1: tsbid
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* %o2: num ttes
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*
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* returns %o0: num ttes demapped
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*/
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.globl pci_sun4v_iommu_demap
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pci_sun4v_iommu_demap:
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mov %o2, %o3
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mov %o1, %o2
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mov %o0, %o1
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mov HV_FAST_PCI_IOMMU_DEMAP, %o0
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ta HV_FAST_TRAP
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retl
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mov %o1, %o0
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@ -139,6 +139,9 @@ struct pci_pbm_info {
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/* Opaque 32-bit system bus Port ID. */
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u32 portid;
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/* Opaque 32-bit handle used for hypervisor calls. */
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u32 devhandle;
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/* Chipset version information. */
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int chip_type;
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#define PBM_CHIP_TYPE_SABRE 1
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