Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (27 commits) gpu/stub: fix acpi_video build error, fix stub kconfig dependencies drm/radeon/kms: dynamically allocate power state space drm/radeon/kms: fix s/r issues with bios scratch regs agp: ensure GART has an address before enabling it Revert "agp: AMD AGP is used on UP1100 & UP1500 alpha boxen" amd-k7-agp: remove non-x86 code drm/radeon/kms/evergreen: always set certain VGT regs at CP init drm/radeon/kms: add updated ib_execute function for evergreen drm/radeon: remove 0x4243 pci id drm/radeon/kms: Enable new pll calculation for avivo+ asics drm/radeon/kms: add new pll algo for avivo asics drm/radeon/kms: add pll debugging output drm/radeon/kms: switch back to min->max pll post divider iteration drm/radeon/kms: rv6xx+ thermal sensor fixes drm/nv50: fix display on 0x50 drm/nouveau: correctly pair hwmon_init and hwmon_fini drm/i915: Only bind to function 0 of the PCI device drm/i915: Suppress spurious vblank interrupts drm: Avoid leak of adjusted mode along quick set_mode paths drm: Simplify and defend later checks when disabling a crtc ...
This commit is contained in:
commit
bb5b583b52
|
@ -50,7 +50,7 @@ config AGP_ATI
|
|||
|
||||
config AGP_AMD
|
||||
tristate "AMD Irongate, 761, and 762 chipset support"
|
||||
depends on AGP && (X86_32 || ALPHA)
|
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depends on AGP && X86_32
|
||||
help
|
||||
This option gives you AGP support for the GLX component of
|
||||
X on AMD Irongate, 761, and 762 chipsets.
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||||
|
|
|
@ -41,22 +41,8 @@ static int amd_create_page_map(struct amd_page_map *page_map)
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if (page_map->real == NULL)
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return -ENOMEM;
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#ifndef CONFIG_X86
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SetPageReserved(virt_to_page(page_map->real));
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global_cache_flush();
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page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real),
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PAGE_SIZE);
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if (page_map->remapped == NULL) {
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ClearPageReserved(virt_to_page(page_map->real));
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free_page((unsigned long) page_map->real);
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page_map->real = NULL;
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return -ENOMEM;
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}
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global_cache_flush();
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#else
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set_memory_uc((unsigned long)page_map->real, 1);
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page_map->remapped = page_map->real;
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#endif
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for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
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writel(agp_bridge->scratch_page, page_map->remapped+i);
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@ -68,12 +54,7 @@ static int amd_create_page_map(struct amd_page_map *page_map)
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static void amd_free_page_map(struct amd_page_map *page_map)
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{
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#ifndef CONFIG_X86
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iounmap(page_map->remapped);
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ClearPageReserved(virt_to_page(page_map->real));
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#else
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set_memory_wb((unsigned long)page_map->real, 1);
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#endif
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free_page((unsigned long) page_map->real);
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}
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|
|
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@ -773,21 +773,15 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev,
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dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
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/*
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* If the device has not been properly setup, the following will catch
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* the problem and should stop the system from crashing.
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* 20030610 - hamish@zot.org
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*/
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if (pci_enable_device(pdev)) {
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dev_err(&pdev->dev, "can't enable PCI device\n");
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agp_put_bridge(bridge);
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return -ENODEV;
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}
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/*
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* The following fixes the case where the BIOS has "forgotten" to
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* provide an address range for the GART.
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* 20030610 - hamish@zot.org
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* This happens before pci_enable_device() intentionally;
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* calling pci_enable_device() before assigning the resource
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* will result in the GART being disabled on machines with such
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* BIOSs (the GART ends up with a BAR starting at 0, which
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* conflicts a lot of other devices).
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*/
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r = &pdev->resource[0];
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if (!r->start && r->end) {
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@ -798,6 +792,17 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev,
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}
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}
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/*
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* If the device has not been properly setup, the following will catch
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* the problem and should stop the system from crashing.
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* 20030610 - hamish@zot.org
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*/
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if (pci_enable_device(pdev)) {
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dev_err(&pdev->dev, "can't enable PCI device\n");
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agp_put_bridge(bridge);
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return -ENODEV;
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}
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|
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/* Fill in the mode register */
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if (cap_ptr) {
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pci_read_config_dword(pdev,
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|
|
|
@ -2674,3 +2674,23 @@ out:
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mutex_unlock(&dev->mode_config.mutex);
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return ret;
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}
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|
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void drm_mode_config_reset(struct drm_device *dev)
|
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{
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struct drm_crtc *crtc;
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struct drm_encoder *encoder;
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struct drm_connector *connector;
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|
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
|
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if (crtc->funcs->reset)
|
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crtc->funcs->reset(crtc);
|
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|
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
|
||||
if (encoder->funcs->reset)
|
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encoder->funcs->reset(encoder);
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|
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list_for_each_entry(connector, &dev->mode_config.connector_list, head)
|
||||
if (connector->funcs->reset)
|
||||
connector->funcs->reset(connector);
|
||||
}
|
||||
EXPORT_SYMBOL(drm_mode_config_reset);
|
||||
|
|
|
@ -343,13 +343,12 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
|
|||
struct drm_encoder *encoder;
|
||||
bool ret = true;
|
||||
|
||||
adjusted_mode = drm_mode_duplicate(dev, mode);
|
||||
|
||||
crtc->enabled = drm_helper_crtc_in_use(crtc);
|
||||
|
||||
if (!crtc->enabled)
|
||||
return true;
|
||||
|
||||
adjusted_mode = drm_mode_duplicate(dev, mode);
|
||||
|
||||
saved_hwmode = crtc->hwmode;
|
||||
saved_mode = crtc->mode;
|
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saved_x = crtc->x;
|
||||
|
@ -437,10 +436,9 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
|
|||
*/
|
||||
drm_calc_timestamping_constants(crtc);
|
||||
|
||||
/* XXX free adjustedmode */
|
||||
drm_mode_destroy(dev, adjusted_mode);
|
||||
/* FIXME: add subpixel order */
|
||||
done:
|
||||
drm_mode_destroy(dev, adjusted_mode);
|
||||
if (!ret) {
|
||||
crtc->hwmode = saved_hwmode;
|
||||
crtc->mode = saved_mode;
|
||||
|
@ -497,14 +495,17 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
|
|||
|
||||
crtc_funcs = set->crtc->helper_private;
|
||||
|
||||
if (!set->mode)
|
||||
set->fb = NULL;
|
||||
|
||||
if (set->fb) {
|
||||
DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
|
||||
set->crtc->base.id, set->fb->base.id,
|
||||
(int)set->num_connectors, set->x, set->y);
|
||||
} else {
|
||||
DRM_DEBUG_KMS("[CRTC:%d] [NOFB] #connectors=%d (x y) (%i %i)\n",
|
||||
set->crtc->base.id, (int)set->num_connectors,
|
||||
set->x, set->y);
|
||||
DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
|
||||
set->mode = NULL;
|
||||
set->num_connectors = 0;
|
||||
}
|
||||
|
||||
dev = set->crtc->dev;
|
||||
|
@ -649,8 +650,8 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
|
|||
mode_changed = true;
|
||||
|
||||
if (mode_changed) {
|
||||
set->crtc->enabled = (set->mode != NULL);
|
||||
if (set->mode != NULL) {
|
||||
set->crtc->enabled = drm_helper_crtc_in_use(set->crtc);
|
||||
if (set->crtc->enabled) {
|
||||
DRM_DEBUG_KMS("attempting to set mode from"
|
||||
" userspace\n");
|
||||
drm_mode_debug_printmodeline(set->mode);
|
||||
|
|
|
@ -1250,7 +1250,7 @@ void drm_handle_vblank_events(struct drm_device *dev, int crtc)
|
|||
* Drivers should call this routine in their vblank interrupt handlers to
|
||||
* update the vblank counter and send any signals that may be pending.
|
||||
*/
|
||||
void drm_handle_vblank(struct drm_device *dev, int crtc)
|
||||
bool drm_handle_vblank(struct drm_device *dev, int crtc)
|
||||
{
|
||||
u32 vblcount;
|
||||
s64 diff_ns;
|
||||
|
@ -1258,7 +1258,7 @@ void drm_handle_vblank(struct drm_device *dev, int crtc)
|
|||
unsigned long irqflags;
|
||||
|
||||
if (!dev->num_crtcs)
|
||||
return;
|
||||
return false;
|
||||
|
||||
/* Need timestamp lock to prevent concurrent execution with
|
||||
* vblank enable/disable, as this would cause inconsistent
|
||||
|
@ -1269,7 +1269,7 @@ void drm_handle_vblank(struct drm_device *dev, int crtc)
|
|||
/* Vblank irq handling disabled. Nothing to do. */
|
||||
if (!dev->vblank_enabled[crtc]) {
|
||||
spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
|
||||
return;
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Fetch corresponding timestamp for this vblank interval from
|
||||
|
@ -1311,5 +1311,6 @@ void drm_handle_vblank(struct drm_device *dev, int crtc)
|
|||
drm_handle_vblank_events(dev, crtc);
|
||||
|
||||
spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
|
||||
return true;
|
||||
}
|
||||
EXPORT_SYMBOL(drm_handle_vblank);
|
||||
|
|
|
@ -354,6 +354,7 @@ static int i915_drm_thaw(struct drm_device *dev)
|
|||
error = i915_gem_init_ringbuffer(dev);
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
|
||||
drm_mode_config_reset(dev);
|
||||
drm_irq_install(dev);
|
||||
|
||||
/* Resume the modeset for every activated CRTC */
|
||||
|
@ -542,6 +543,7 @@ int i915_reset(struct drm_device *dev, u8 flags)
|
|||
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
drm_irq_uninstall(dev);
|
||||
drm_mode_config_reset(dev);
|
||||
drm_irq_install(dev);
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
}
|
||||
|
@ -566,6 +568,14 @@ int i915_reset(struct drm_device *dev, u8 flags)
|
|||
static int __devinit
|
||||
i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
/* Only bind to function 0 of the device. Early generations
|
||||
* used function 1 as a placeholder for multi-head. This causes
|
||||
* us confusion instead, especially on the systems where both
|
||||
* functions have the same PCI-ID!
|
||||
*/
|
||||
if (PCI_FUNC(pdev->devfn))
|
||||
return -ENODEV;
|
||||
|
||||
return drm_get_pci_dev(pdev, ent, &driver);
|
||||
}
|
||||
|
||||
|
|
|
@ -1196,18 +1196,18 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
|
|||
intel_finish_page_flip_plane(dev, 1);
|
||||
}
|
||||
|
||||
if (pipea_stats & vblank_status) {
|
||||
if (pipea_stats & vblank_status &&
|
||||
drm_handle_vblank(dev, 0)) {
|
||||
vblank++;
|
||||
drm_handle_vblank(dev, 0);
|
||||
if (!dev_priv->flip_pending_is_done) {
|
||||
i915_pageflip_stall_check(dev, 0);
|
||||
intel_finish_page_flip(dev, 0);
|
||||
}
|
||||
}
|
||||
|
||||
if (pipeb_stats & vblank_status) {
|
||||
if (pipeb_stats & vblank_status &&
|
||||
drm_handle_vblank(dev, 1)) {
|
||||
vblank++;
|
||||
drm_handle_vblank(dev, 1);
|
||||
if (!dev_priv->flip_pending_is_done) {
|
||||
i915_pageflip_stall_check(dev, 1);
|
||||
intel_finish_page_flip(dev, 1);
|
||||
|
|
|
@ -535,6 +535,15 @@ static int intel_crt_set_property(struct drm_connector *connector,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void intel_crt_reset(struct drm_connector *connector)
|
||||
{
|
||||
struct drm_device *dev = connector->dev;
|
||||
struct intel_crt *crt = intel_attached_crt(connector);
|
||||
|
||||
if (HAS_PCH_SPLIT(dev))
|
||||
crt->force_hotplug_required = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Routines for controlling stuff on the analog port
|
||||
*/
|
||||
|
@ -548,6 +557,7 @@ static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
|
|||
};
|
||||
|
||||
static const struct drm_connector_funcs intel_crt_connector_funcs = {
|
||||
.reset = intel_crt_reset,
|
||||
.dpms = drm_helper_connector_dpms,
|
||||
.detect = intel_crt_detect,
|
||||
.fill_modes = drm_helper_probe_single_connector_modes,
|
||||
|
|
|
@ -5551,6 +5551,18 @@ cleanup_work:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void intel_crtc_reset(struct drm_crtc *crtc)
|
||||
{
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
||||
|
||||
/* Reset flags back to the 'unknown' status so that they
|
||||
* will be correctly set on the initial modeset.
|
||||
*/
|
||||
intel_crtc->cursor_addr = 0;
|
||||
intel_crtc->dpms_mode = -1;
|
||||
intel_crtc->active = true; /* force the pipe off on setup_init_config */
|
||||
}
|
||||
|
||||
static struct drm_crtc_helper_funcs intel_helper_funcs = {
|
||||
.dpms = intel_crtc_dpms,
|
||||
.mode_fixup = intel_crtc_mode_fixup,
|
||||
|
@ -5562,6 +5574,7 @@ static struct drm_crtc_helper_funcs intel_helper_funcs = {
|
|||
};
|
||||
|
||||
static const struct drm_crtc_funcs intel_crtc_funcs = {
|
||||
.reset = intel_crtc_reset,
|
||||
.cursor_set = intel_crtc_cursor_set,
|
||||
.cursor_move = intel_crtc_cursor_move,
|
||||
.gamma_set = intel_crtc_gamma_set,
|
||||
|
@ -5652,9 +5665,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
|
|||
dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
|
||||
dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
|
||||
|
||||
intel_crtc->cursor_addr = 0;
|
||||
intel_crtc->dpms_mode = -1;
|
||||
intel_crtc->active = true; /* force the pipe off on setup_init_config */
|
||||
intel_crtc_reset(&intel_crtc->base);
|
||||
|
||||
if (HAS_PCH_SPLIT(dev)) {
|
||||
intel_helper_funcs.prepare = ironlake_crtc_prepare;
|
||||
|
|
|
@ -473,20 +473,6 @@ static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
|
|||
return false;
|
||||
}
|
||||
|
||||
i = 3;
|
||||
while (status == SDVO_CMD_STATUS_PENDING && i--) {
|
||||
if (!intel_sdvo_read_byte(intel_sdvo,
|
||||
SDVO_I2C_CMD_STATUS,
|
||||
&status))
|
||||
return false;
|
||||
}
|
||||
if (status != SDVO_CMD_STATUS_SUCCESS) {
|
||||
DRM_DEBUG_KMS("command returns response %s [%d]\n",
|
||||
status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP ? cmd_status_names[status] : "???",
|
||||
status);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
@ -497,6 +483,8 @@ static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
|
|||
u8 status;
|
||||
int i;
|
||||
|
||||
DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
|
||||
|
||||
/*
|
||||
* The documentation states that all commands will be
|
||||
* processed within 15µs, and that we need only poll
|
||||
|
@ -505,14 +493,19 @@ static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
|
|||
*
|
||||
* Check 5 times in case the hardware failed to read the docs.
|
||||
*/
|
||||
do {
|
||||
if (!intel_sdvo_read_byte(intel_sdvo,
|
||||
SDVO_I2C_CMD_STATUS,
|
||||
&status))
|
||||
goto log_fail;
|
||||
|
||||
while (status == SDVO_CMD_STATUS_PENDING && retry--) {
|
||||
udelay(15);
|
||||
if (!intel_sdvo_read_byte(intel_sdvo,
|
||||
SDVO_I2C_CMD_STATUS,
|
||||
&status))
|
||||
return false;
|
||||
} while (status == SDVO_CMD_STATUS_PENDING && --retry);
|
||||
goto log_fail;
|
||||
}
|
||||
|
||||
DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
|
||||
if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
|
||||
DRM_LOG_KMS("(%s)", cmd_status_names[status]);
|
||||
else
|
||||
|
@ -533,7 +526,7 @@ static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
|
|||
return true;
|
||||
|
||||
log_fail:
|
||||
DRM_LOG_KMS("\n");
|
||||
DRM_LOG_KMS("... failed\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
|
@ -550,6 +543,7 @@ static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
|
|||
static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
|
||||
u8 ddc_bus)
|
||||
{
|
||||
/* This must be the immediately preceding write before the i2c xfer */
|
||||
return intel_sdvo_write_cmd(intel_sdvo,
|
||||
SDVO_CMD_SET_CONTROL_BUS_SWITCH,
|
||||
&ddc_bus, 1);
|
||||
|
@ -557,7 +551,10 @@ static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
|
|||
|
||||
static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
|
||||
{
|
||||
return intel_sdvo_write_cmd(intel_sdvo, cmd, data, len);
|
||||
if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
|
||||
return false;
|
||||
|
||||
return intel_sdvo_read_response(intel_sdvo, NULL, 0);
|
||||
}
|
||||
|
||||
static bool
|
||||
|
@ -859,18 +856,21 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
|
|||
|
||||
intel_dip_infoframe_csum(&avi_if);
|
||||
|
||||
if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX,
|
||||
if (!intel_sdvo_set_value(intel_sdvo,
|
||||
SDVO_CMD_SET_HBUF_INDEX,
|
||||
set_buf_index, 2))
|
||||
return false;
|
||||
|
||||
for (i = 0; i < sizeof(avi_if); i += 8) {
|
||||
if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA,
|
||||
if (!intel_sdvo_set_value(intel_sdvo,
|
||||
SDVO_CMD_SET_HBUF_DATA,
|
||||
data, 8))
|
||||
return false;
|
||||
data++;
|
||||
}
|
||||
|
||||
return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE,
|
||||
return intel_sdvo_set_value(intel_sdvo,
|
||||
SDVO_CMD_SET_HBUF_TXRATE,
|
||||
&tx_rate, 1);
|
||||
}
|
||||
|
||||
|
|
|
@ -443,7 +443,7 @@ nouveau_hwmon_fini(struct drm_device *dev)
|
|||
struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
|
||||
|
||||
if (pm->hwmon) {
|
||||
sysfs_remove_group(&pm->hwmon->kobj, &hwmon_attrgroup);
|
||||
sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_attrgroup);
|
||||
hwmon_device_unregister(pm->hwmon);
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -283,8 +283,7 @@ nv50_evo_create(struct drm_device *dev)
|
|||
nv50_evo_channel_del(&dev_priv->evo);
|
||||
return ret;
|
||||
}
|
||||
} else
|
||||
if (dev_priv->chipset != 0x50) {
|
||||
} else {
|
||||
ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB16, 0x70, 0x19,
|
||||
0, 0xffffffff, 0x00010000);
|
||||
if (ret) {
|
||||
|
|
|
@ -555,6 +555,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
|
|||
dp_clock = dig_connector->dp_clock;
|
||||
}
|
||||
}
|
||||
/* this might work properly with the new pll algo */
|
||||
#if 0 /* doesn't work properly on some laptops */
|
||||
/* use recommended ref_div for ss */
|
||||
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
|
||||
|
@ -572,6 +573,11 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
|
|||
adjusted_clock = mode->clock * 2;
|
||||
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
|
||||
pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
|
||||
/* rv515 needs more testing with this option */
|
||||
if (rdev->family != CHIP_RV515) {
|
||||
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
|
||||
pll->flags |= RADEON_PLL_IS_LCD;
|
||||
}
|
||||
} else {
|
||||
if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
|
||||
pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
|
||||
|
@ -951,8 +957,16 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
|
|||
/* adjust pixel clock as needed */
|
||||
adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
|
||||
|
||||
radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
|
||||
&ref_div, &post_div);
|
||||
/* rv515 seems happier with the old algo */
|
||||
if (rdev->family == CHIP_RV515)
|
||||
radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
|
||||
&ref_div, &post_div);
|
||||
else if (ASIC_IS_AVIVO(rdev))
|
||||
radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
|
||||
&ref_div, &post_div);
|
||||
else
|
||||
radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
|
||||
&ref_div, &post_div);
|
||||
|
||||
atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
|
||||
|
||||
|
|
|
@ -97,26 +97,29 @@ u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
|
|||
}
|
||||
|
||||
/* get temperature in millidegrees */
|
||||
u32 evergreen_get_temp(struct radeon_device *rdev)
|
||||
int evergreen_get_temp(struct radeon_device *rdev)
|
||||
{
|
||||
u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
|
||||
ASIC_T_SHIFT;
|
||||
u32 actual_temp = 0;
|
||||
|
||||
if ((temp >> 10) & 1)
|
||||
actual_temp = 0;
|
||||
else if ((temp >> 9) & 1)
|
||||
if (temp & 0x400)
|
||||
actual_temp = -256;
|
||||
else if (temp & 0x200)
|
||||
actual_temp = 255;
|
||||
else
|
||||
actual_temp = (temp >> 1) & 0xff;
|
||||
else if (temp & 0x100) {
|
||||
actual_temp = temp & 0x1ff;
|
||||
actual_temp |= ~0x1ff;
|
||||
} else
|
||||
actual_temp = temp & 0xff;
|
||||
|
||||
return actual_temp * 1000;
|
||||
return (actual_temp * 1000) / 2;
|
||||
}
|
||||
|
||||
u32 sumo_get_temp(struct radeon_device *rdev)
|
||||
int sumo_get_temp(struct radeon_device *rdev)
|
||||
{
|
||||
u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
|
||||
u32 actual_temp = (temp >> 1) & 0xff;
|
||||
int actual_temp = temp - 49;
|
||||
|
||||
return actual_temp * 1000;
|
||||
}
|
||||
|
@ -1182,6 +1185,18 @@ static void evergreen_mc_program(struct radeon_device *rdev)
|
|||
/*
|
||||
* CP.
|
||||
*/
|
||||
void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
|
||||
{
|
||||
/* set to DX10/11 mode */
|
||||
radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
|
||||
radeon_ring_write(rdev, 1);
|
||||
/* FIXME: implement */
|
||||
radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
|
||||
radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
|
||||
radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
|
||||
radeon_ring_write(rdev, ib->length_dw);
|
||||
}
|
||||
|
||||
|
||||
static int evergreen_cp_load_microcode(struct radeon_device *rdev)
|
||||
{
|
||||
|
@ -1233,7 +1248,7 @@ static int evergreen_cp_start(struct radeon_device *rdev)
|
|||
cp_me = 0xff;
|
||||
WREG32(CP_ME_CNTL, cp_me);
|
||||
|
||||
r = radeon_ring_lock(rdev, evergreen_default_size + 15);
|
||||
r = radeon_ring_lock(rdev, evergreen_default_size + 19);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
|
||||
return r;
|
||||
|
@ -1266,6 +1281,11 @@ static int evergreen_cp_start(struct radeon_device *rdev)
|
|||
radeon_ring_write(rdev, 0xffffffff);
|
||||
radeon_ring_write(rdev, 0xffffffff);
|
||||
|
||||
radeon_ring_write(rdev, 0xc0026900);
|
||||
radeon_ring_write(rdev, 0x00000316);
|
||||
radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
|
||||
radeon_ring_write(rdev, 0x00000010); /* */
|
||||
|
||||
radeon_ring_unlock_commit(rdev);
|
||||
|
||||
return 0;
|
||||
|
@ -2072,6 +2092,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
|
|||
WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
|
||||
|
||||
WREG32(VGT_GS_VERTEX_REUSE, 16);
|
||||
WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
|
||||
WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
|
||||
|
||||
WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
|
||||
|
|
|
@ -232,7 +232,7 @@ draw_auto(struct radeon_device *rdev)
|
|||
|
||||
}
|
||||
|
||||
/* emits 34 */
|
||||
/* emits 36 */
|
||||
static void
|
||||
set_default_state(struct radeon_device *rdev)
|
||||
{
|
||||
|
@ -499,6 +499,10 @@ set_default_state(struct radeon_device *rdev)
|
|||
radeon_ring_write(rdev, 0x00000000);
|
||||
radeon_ring_write(rdev, 0x00000000);
|
||||
|
||||
/* set to DX10/11 mode */
|
||||
radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
|
||||
radeon_ring_write(rdev, 1);
|
||||
|
||||
/* emit an IB pointing at default state */
|
||||
dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
|
||||
gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
|
||||
|
@ -679,7 +683,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
|
|||
/* calculate number of loops correctly */
|
||||
ring_size = num_loops * dwords_per_loop;
|
||||
/* set default + shaders */
|
||||
ring_size += 50; /* shaders + def state */
|
||||
ring_size += 52; /* shaders + def state */
|
||||
ring_size += 10; /* fence emit for VB IB */
|
||||
ring_size += 5; /* done copy */
|
||||
ring_size += 10; /* fence emit for done copy */
|
||||
|
@ -687,7 +691,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
|
|||
if (r)
|
||||
return r;
|
||||
|
||||
set_default_state(rdev); /* 34 */
|
||||
set_default_state(rdev); /* 36 */
|
||||
set_shaders(rdev); /* 16 */
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -240,6 +240,7 @@
|
|||
#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
|
||||
#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
|
||||
#define PA_SC_LINE_STIPPLE 0x28A0C
|
||||
#define PA_SU_LINE_STIPPLE_VALUE 0x8A60
|
||||
#define PA_SC_LINE_STIPPLE_STATE 0x8B10
|
||||
|
||||
#define SCRATCH_REG0 0x8500
|
||||
|
@ -652,6 +653,7 @@
|
|||
#define PACKET3_DISPATCH_DIRECT 0x15
|
||||
#define PACKET3_DISPATCH_INDIRECT 0x16
|
||||
#define PACKET3_INDIRECT_BUFFER_END 0x17
|
||||
#define PACKET3_MODE_CONTROL 0x18
|
||||
#define PACKET3_SET_PREDICATION 0x20
|
||||
#define PACKET3_REG_RMW 0x21
|
||||
#define PACKET3_COND_EXEC 0x22
|
||||
|
|
|
@ -97,12 +97,16 @@ void r600_irq_disable(struct radeon_device *rdev);
|
|||
static void r600_pcie_gen2_enable(struct radeon_device *rdev);
|
||||
|
||||
/* get temperature in millidegrees */
|
||||
u32 rv6xx_get_temp(struct radeon_device *rdev)
|
||||
int rv6xx_get_temp(struct radeon_device *rdev)
|
||||
{
|
||||
u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
|
||||
ASIC_T_SHIFT;
|
||||
int actual_temp = temp & 0xff;
|
||||
|
||||
return temp * 1000;
|
||||
if (temp & 0x100)
|
||||
actual_temp -= 256;
|
||||
|
||||
return actual_temp * 1000;
|
||||
}
|
||||
|
||||
void r600_pm_get_dynpm_state(struct radeon_device *rdev)
|
||||
|
|
|
@ -179,10 +179,10 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev);
|
|||
void radeon_atombios_get_power_modes(struct radeon_device *rdev);
|
||||
void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
|
||||
void rs690_pm_info(struct radeon_device *rdev);
|
||||
extern u32 rv6xx_get_temp(struct radeon_device *rdev);
|
||||
extern u32 rv770_get_temp(struct radeon_device *rdev);
|
||||
extern u32 evergreen_get_temp(struct radeon_device *rdev);
|
||||
extern u32 sumo_get_temp(struct radeon_device *rdev);
|
||||
extern int rv6xx_get_temp(struct radeon_device *rdev);
|
||||
extern int rv770_get_temp(struct radeon_device *rdev);
|
||||
extern int evergreen_get_temp(struct radeon_device *rdev);
|
||||
extern int sumo_get_temp(struct radeon_device *rdev);
|
||||
|
||||
/*
|
||||
* Fences.
|
||||
|
@ -812,8 +812,7 @@ struct radeon_pm {
|
|||
fixed20_12 sclk;
|
||||
fixed20_12 mclk;
|
||||
fixed20_12 needed_bandwidth;
|
||||
/* XXX: use a define for num power modes */
|
||||
struct radeon_power_state power_state[8];
|
||||
struct radeon_power_state *power_state;
|
||||
/* number of valid power states */
|
||||
int num_power_states;
|
||||
int current_power_state_index;
|
||||
|
|
|
@ -759,7 +759,7 @@ static struct radeon_asic evergreen_asic = {
|
|||
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
|
||||
.gart_set_page = &rs600_gart_set_page,
|
||||
.ring_test = &r600_ring_test,
|
||||
.ring_ib_execute = &r600_ring_ib_execute,
|
||||
.ring_ib_execute = &evergreen_ring_ib_execute,
|
||||
.irq_set = &evergreen_irq_set,
|
||||
.irq_process = &evergreen_irq_process,
|
||||
.get_vblank_counter = &evergreen_get_vblank_counter,
|
||||
|
@ -805,7 +805,7 @@ static struct radeon_asic sumo_asic = {
|
|||
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
|
||||
.gart_set_page = &rs600_gart_set_page,
|
||||
.ring_test = &r600_ring_test,
|
||||
.ring_ib_execute = &r600_ring_ib_execute,
|
||||
.ring_ib_execute = &evergreen_ring_ib_execute,
|
||||
.irq_set = &evergreen_irq_set,
|
||||
.irq_process = &evergreen_irq_process,
|
||||
.get_vblank_counter = &evergreen_get_vblank_counter,
|
||||
|
@ -848,7 +848,7 @@ static struct radeon_asic btc_asic = {
|
|||
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
|
||||
.gart_set_page = &rs600_gart_set_page,
|
||||
.ring_test = &r600_ring_test,
|
||||
.ring_ib_execute = &r600_ring_ib_execute,
|
||||
.ring_ib_execute = &evergreen_ring_ib_execute,
|
||||
.irq_set = &evergreen_irq_set,
|
||||
.irq_process = &evergreen_irq_process,
|
||||
.get_vblank_counter = &evergreen_get_vblank_counter,
|
||||
|
|
|
@ -355,6 +355,7 @@ int evergreen_resume(struct radeon_device *rdev);
|
|||
bool evergreen_gpu_is_lockup(struct radeon_device *rdev);
|
||||
int evergreen_asic_reset(struct radeon_device *rdev);
|
||||
void evergreen_bandwidth_update(struct radeon_device *rdev);
|
||||
void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
|
||||
int evergreen_copy_blit(struct radeon_device *rdev,
|
||||
uint64_t src_offset, uint64_t dst_offset,
|
||||
unsigned num_pages, struct radeon_fence *fence);
|
||||
|
|
|
@ -1163,16 +1163,6 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
|
|||
p1pll->pll_out_min = 64800;
|
||||
else
|
||||
p1pll->pll_out_min = 20000;
|
||||
} else if (p1pll->pll_out_min > 64800) {
|
||||
/* Limiting the pll output range is a good thing generally as
|
||||
* it limits the number of possible pll combinations for a given
|
||||
* frequency presumably to the ones that work best on each card.
|
||||
* However, certain duallink DVI monitors seem to like
|
||||
* pll combinations that would be limited by this at least on
|
||||
* pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
|
||||
* family.
|
||||
*/
|
||||
p1pll->pll_out_min = 64800;
|
||||
}
|
||||
|
||||
p1pll->pll_in_min =
|
||||
|
@ -1987,6 +1977,9 @@ static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
|
|||
num_modes = power_info->info.ucNumOfPowerModeEntries;
|
||||
if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
|
||||
num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
|
||||
rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
|
||||
if (!rdev->pm.power_state)
|
||||
return state_index;
|
||||
/* last mode is usually default, array is low to high */
|
||||
for (i = 0; i < num_modes; i++) {
|
||||
rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
|
||||
|
@ -2338,6 +2331,10 @@ static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
|
|||
power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
|
||||
|
||||
radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
|
||||
rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
|
||||
power_info->pplib.ucNumStates, GFP_KERNEL);
|
||||
if (!rdev->pm.power_state)
|
||||
return state_index;
|
||||
/* first mode is usually default, followed by low to high */
|
||||
for (i = 0; i < power_info->pplib.ucNumStates; i++) {
|
||||
mode_index = 0;
|
||||
|
@ -2418,6 +2415,10 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
|
|||
non_clock_info_array = (struct NonClockInfoArray *)
|
||||
(mode_info->atom_context->bios + data_offset +
|
||||
power_info->pplib.usNonClockInfoArrayOffset);
|
||||
rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
|
||||
state_array->ucNumEntries, GFP_KERNEL);
|
||||
if (!rdev->pm.power_state)
|
||||
return state_index;
|
||||
for (i = 0; i < state_array->ucNumEntries; i++) {
|
||||
mode_index = 0;
|
||||
power_state = (union pplib_power_state *)&state_array->states[i];
|
||||
|
@ -2491,19 +2492,22 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
|
|||
break;
|
||||
}
|
||||
} else {
|
||||
/* add the default mode */
|
||||
rdev->pm.power_state[state_index].type =
|
||||
POWER_STATE_TYPE_DEFAULT;
|
||||
rdev->pm.power_state[state_index].num_clock_modes = 1;
|
||||
rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
|
||||
rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
|
||||
rdev->pm.power_state[state_index].default_clock_mode =
|
||||
&rdev->pm.power_state[state_index].clock_info[0];
|
||||
rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
|
||||
rdev->pm.power_state[state_index].pcie_lanes = 16;
|
||||
rdev->pm.default_power_state_index = state_index;
|
||||
rdev->pm.power_state[state_index].flags = 0;
|
||||
state_index++;
|
||||
rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
|
||||
if (rdev->pm.power_state) {
|
||||
/* add the default mode */
|
||||
rdev->pm.power_state[state_index].type =
|
||||
POWER_STATE_TYPE_DEFAULT;
|
||||
rdev->pm.power_state[state_index].num_clock_modes = 1;
|
||||
rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
|
||||
rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
|
||||
rdev->pm.power_state[state_index].default_clock_mode =
|
||||
&rdev->pm.power_state[state_index].clock_info[0];
|
||||
rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
|
||||
rdev->pm.power_state[state_index].pcie_lanes = 16;
|
||||
rdev->pm.default_power_state_index = state_index;
|
||||
rdev->pm.power_state[state_index].flags = 0;
|
||||
state_index++;
|
||||
}
|
||||
}
|
||||
|
||||
rdev->pm.num_power_states = state_index;
|
||||
|
@ -2619,7 +2623,7 @@ void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
|
|||
bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
|
||||
|
||||
/* tell the bios not to handle mode switching */
|
||||
bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
|
||||
bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
|
||||
|
||||
if (rdev->family >= CHIP_R600) {
|
||||
WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
|
||||
|
@ -2670,10 +2674,13 @@ void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
|
|||
else
|
||||
bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
|
||||
|
||||
if (lock)
|
||||
if (lock) {
|
||||
bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
|
||||
else
|
||||
bios_6_scratch &= ~ATOM_S6_ACC_MODE;
|
||||
} else {
|
||||
bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
|
||||
bios_6_scratch |= ATOM_S6_ACC_MODE;
|
||||
}
|
||||
|
||||
if (rdev->family >= CHIP_R600)
|
||||
WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
|
||||
|
|
|
@ -2442,6 +2442,17 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev)
|
|||
|
||||
rdev->pm.default_power_state_index = -1;
|
||||
|
||||
/* allocate 2 power states */
|
||||
rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
|
||||
if (!rdev->pm.power_state) {
|
||||
rdev->pm.default_power_state_index = state_index;
|
||||
rdev->pm.num_power_states = 0;
|
||||
|
||||
rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
|
||||
rdev->pm.current_clock_mode_index = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
if (rdev->flags & RADEON_IS_MOBILITY) {
|
||||
offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
|
||||
if (offset) {
|
||||
|
|
|
@ -780,6 +780,115 @@ static int radeon_ddc_dump(struct drm_connector *connector)
|
|||
return ret;
|
||||
}
|
||||
|
||||
/* avivo */
|
||||
static void avivo_get_fb_div(struct radeon_pll *pll,
|
||||
u32 target_clock,
|
||||
u32 post_div,
|
||||
u32 ref_div,
|
||||
u32 *fb_div,
|
||||
u32 *frac_fb_div)
|
||||
{
|
||||
u32 tmp = post_div * ref_div;
|
||||
|
||||
tmp *= target_clock;
|
||||
*fb_div = tmp / pll->reference_freq;
|
||||
*frac_fb_div = tmp % pll->reference_freq;
|
||||
}
|
||||
|
||||
static u32 avivo_get_post_div(struct radeon_pll *pll,
|
||||
u32 target_clock)
|
||||
{
|
||||
u32 vco, post_div, tmp;
|
||||
|
||||
if (pll->flags & RADEON_PLL_USE_POST_DIV)
|
||||
return pll->post_div;
|
||||
|
||||
if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
|
||||
if (pll->flags & RADEON_PLL_IS_LCD)
|
||||
vco = pll->lcd_pll_out_min;
|
||||
else
|
||||
vco = pll->pll_out_min;
|
||||
} else {
|
||||
if (pll->flags & RADEON_PLL_IS_LCD)
|
||||
vco = pll->lcd_pll_out_max;
|
||||
else
|
||||
vco = pll->pll_out_max;
|
||||
}
|
||||
|
||||
post_div = vco / target_clock;
|
||||
tmp = vco % target_clock;
|
||||
|
||||
if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
|
||||
if (tmp)
|
||||
post_div++;
|
||||
} else {
|
||||
if (!tmp)
|
||||
post_div--;
|
||||
}
|
||||
|
||||
return post_div;
|
||||
}
|
||||
|
||||
#define MAX_TOLERANCE 10
|
||||
|
||||
void radeon_compute_pll_avivo(struct radeon_pll *pll,
|
||||
u32 freq,
|
||||
u32 *dot_clock_p,
|
||||
u32 *fb_div_p,
|
||||
u32 *frac_fb_div_p,
|
||||
u32 *ref_div_p,
|
||||
u32 *post_div_p)
|
||||
{
|
||||
u32 target_clock = freq / 10;
|
||||
u32 post_div = avivo_get_post_div(pll, target_clock);
|
||||
u32 ref_div = pll->min_ref_div;
|
||||
u32 fb_div = 0, frac_fb_div = 0, tmp;
|
||||
|
||||
if (pll->flags & RADEON_PLL_USE_REF_DIV)
|
||||
ref_div = pll->reference_div;
|
||||
|
||||
if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
|
||||
avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
|
||||
frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
|
||||
if (frac_fb_div >= 5) {
|
||||
frac_fb_div -= 5;
|
||||
frac_fb_div = frac_fb_div / 10;
|
||||
frac_fb_div++;
|
||||
}
|
||||
if (frac_fb_div >= 10) {
|
||||
fb_div++;
|
||||
frac_fb_div = 0;
|
||||
}
|
||||
} else {
|
||||
while (ref_div <= pll->max_ref_div) {
|
||||
avivo_get_fb_div(pll, target_clock, post_div, ref_div,
|
||||
&fb_div, &frac_fb_div);
|
||||
if (frac_fb_div >= (pll->reference_freq / 2))
|
||||
fb_div++;
|
||||
frac_fb_div = 0;
|
||||
tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
|
||||
tmp = (tmp * 10000) / target_clock;
|
||||
|
||||
if (tmp > (10000 + MAX_TOLERANCE))
|
||||
ref_div++;
|
||||
else if (tmp >= (10000 - MAX_TOLERANCE))
|
||||
break;
|
||||
else
|
||||
ref_div++;
|
||||
}
|
||||
}
|
||||
|
||||
*dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
|
||||
(ref_div * post_div * 10);
|
||||
*fb_div_p = fb_div;
|
||||
*frac_fb_div_p = frac_fb_div;
|
||||
*ref_div_p = ref_div;
|
||||
*post_div_p = post_div;
|
||||
DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
|
||||
*dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
|
||||
}
|
||||
|
||||
/* pre-avivo */
|
||||
static inline uint32_t radeon_div(uint64_t n, uint32_t d)
|
||||
{
|
||||
uint64_t mod;
|
||||
|
@ -790,13 +899,13 @@ static inline uint32_t radeon_div(uint64_t n, uint32_t d)
|
|||
return n;
|
||||
}
|
||||
|
||||
void radeon_compute_pll(struct radeon_pll *pll,
|
||||
uint64_t freq,
|
||||
uint32_t *dot_clock_p,
|
||||
uint32_t *fb_div_p,
|
||||
uint32_t *frac_fb_div_p,
|
||||
uint32_t *ref_div_p,
|
||||
uint32_t *post_div_p)
|
||||
void radeon_compute_pll_legacy(struct radeon_pll *pll,
|
||||
uint64_t freq,
|
||||
uint32_t *dot_clock_p,
|
||||
uint32_t *fb_div_p,
|
||||
uint32_t *frac_fb_div_p,
|
||||
uint32_t *ref_div_p,
|
||||
uint32_t *post_div_p)
|
||||
{
|
||||
uint32_t min_ref_div = pll->min_ref_div;
|
||||
uint32_t max_ref_div = pll->max_ref_div;
|
||||
|
@ -826,6 +935,9 @@ void radeon_compute_pll(struct radeon_pll *pll,
|
|||
pll_out_max = pll->pll_out_max;
|
||||
}
|
||||
|
||||
if (pll_out_min > 64800)
|
||||
pll_out_min = 64800;
|
||||
|
||||
if (pll->flags & RADEON_PLL_USE_REF_DIV)
|
||||
min_ref_div = max_ref_div = pll->reference_div;
|
||||
else {
|
||||
|
@ -849,7 +961,7 @@ void radeon_compute_pll(struct radeon_pll *pll,
|
|||
max_fractional_feed_div = pll->max_frac_feedback_div;
|
||||
}
|
||||
|
||||
for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
|
||||
for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
|
||||
uint32_t ref_div;
|
||||
|
||||
if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
|
||||
|
@ -965,6 +1077,10 @@ void radeon_compute_pll(struct radeon_pll *pll,
|
|||
*frac_fb_div_p = best_frac_feedback_div;
|
||||
*ref_div_p = best_ref_div;
|
||||
*post_div_p = best_post_div;
|
||||
DRM_DEBUG_KMS("%d %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
|
||||
freq, best_freq / 1000, best_feedback_div, best_frac_feedback_div,
|
||||
best_ref_div, best_post_div);
|
||||
|
||||
}
|
||||
|
||||
static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
|
||||
|
|
|
@ -1063,7 +1063,7 @@ atombios_set_edp_panel_power(struct drm_connector *connector, int action)
|
|||
if (!ASIC_IS_DCE4(rdev))
|
||||
return;
|
||||
|
||||
if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) ||
|
||||
if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
|
||||
(action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
|
||||
return;
|
||||
|
||||
|
|
|
@ -778,9 +778,9 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
|
|||
DRM_DEBUG_KMS("\n");
|
||||
|
||||
if (!use_bios_divs) {
|
||||
radeon_compute_pll(pll, mode->clock,
|
||||
&freq, &feedback_div, &frac_fb_div,
|
||||
&reference_div, &post_divider);
|
||||
radeon_compute_pll_legacy(pll, mode->clock,
|
||||
&freq, &feedback_div, &frac_fb_div,
|
||||
&reference_div, &post_divider);
|
||||
|
||||
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
|
||||
if (post_div->divider == post_divider)
|
||||
|
|
|
@ -149,6 +149,7 @@ struct radeon_tmds_pll {
|
|||
#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
|
||||
#define RADEON_PLL_USE_POST_DIV (1 << 12)
|
||||
#define RADEON_PLL_IS_LCD (1 << 13)
|
||||
#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
|
||||
|
||||
struct radeon_pll {
|
||||
/* reference frequency */
|
||||
|
@ -510,13 +511,21 @@ extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
|
|||
struct radeon_atom_ss *ss,
|
||||
int id, u32 clock);
|
||||
|
||||
extern void radeon_compute_pll(struct radeon_pll *pll,
|
||||
uint64_t freq,
|
||||
uint32_t *dot_clock_p,
|
||||
uint32_t *fb_div_p,
|
||||
uint32_t *frac_fb_div_p,
|
||||
uint32_t *ref_div_p,
|
||||
uint32_t *post_div_p);
|
||||
extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
|
||||
uint64_t freq,
|
||||
uint32_t *dot_clock_p,
|
||||
uint32_t *fb_div_p,
|
||||
uint32_t *frac_fb_div_p,
|
||||
uint32_t *ref_div_p,
|
||||
uint32_t *post_div_p);
|
||||
|
||||
extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
|
||||
u32 freq,
|
||||
u32 *dot_clock_p,
|
||||
u32 *fb_div_p,
|
||||
u32 *frac_fb_div_p,
|
||||
u32 *ref_div_p,
|
||||
u32 *post_div_p);
|
||||
|
||||
extern void radeon_setup_encoder_clones(struct drm_device *dev);
|
||||
|
||||
|
|
|
@ -430,7 +430,7 @@ static ssize_t radeon_hwmon_show_temp(struct device *dev,
|
|||
{
|
||||
struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
|
||||
struct radeon_device *rdev = ddev->dev_private;
|
||||
u32 temp;
|
||||
int temp;
|
||||
|
||||
switch (rdev->pm.int_thermal_type) {
|
||||
case THERMAL_TYPE_RV6XX:
|
||||
|
@ -646,6 +646,9 @@ void radeon_pm_fini(struct radeon_device *rdev)
|
|||
#endif
|
||||
}
|
||||
|
||||
if (rdev->pm.power_state)
|
||||
kfree(rdev->pm.power_state);
|
||||
|
||||
radeon_hwmon_fini(rdev);
|
||||
}
|
||||
|
||||
|
|
|
@ -78,18 +78,23 @@ u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
|
|||
}
|
||||
|
||||
/* get temperature in millidegrees */
|
||||
u32 rv770_get_temp(struct radeon_device *rdev)
|
||||
int rv770_get_temp(struct radeon_device *rdev)
|
||||
{
|
||||
u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
|
||||
ASIC_T_SHIFT;
|
||||
u32 actual_temp = 0;
|
||||
int actual_temp;
|
||||
|
||||
if ((temp >> 9) & 1)
|
||||
actual_temp = 0;
|
||||
else
|
||||
actual_temp = (temp >> 1) & 0xff;
|
||||
if (temp & 0x400)
|
||||
actual_temp = -256;
|
||||
else if (temp & 0x200)
|
||||
actual_temp = 255;
|
||||
else if (temp & 0x100) {
|
||||
actual_temp = temp & 0x1ff;
|
||||
actual_temp |= ~0x1ff;
|
||||
} else
|
||||
actual_temp = temp & 0xff;
|
||||
|
||||
return actual_temp * 1000;
|
||||
return (actual_temp * 1000) / 2;
|
||||
}
|
||||
|
||||
void rv770_pm_misc(struct radeon_device *rdev)
|
||||
|
|
|
@ -1367,7 +1367,7 @@ extern int drm_vblank_wait(struct drm_device *dev, unsigned int *vbl_seq);
|
|||
extern u32 drm_vblank_count(struct drm_device *dev, int crtc);
|
||||
extern u32 drm_vblank_count_and_time(struct drm_device *dev, int crtc,
|
||||
struct timeval *vblanktime);
|
||||
extern void drm_handle_vblank(struct drm_device *dev, int crtc);
|
||||
extern bool drm_handle_vblank(struct drm_device *dev, int crtc);
|
||||
extern int drm_vblank_get(struct drm_device *dev, int crtc);
|
||||
extern void drm_vblank_put(struct drm_device *dev, int crtc);
|
||||
extern void drm_vblank_off(struct drm_device *dev, int crtc);
|
||||
|
|
|
@ -275,6 +275,7 @@ struct drm_pending_vblank_event;
|
|||
|
||||
/**
|
||||
* drm_crtc_funcs - control CRTCs for a given device
|
||||
* @reset: reset CRTC after state has been invalidate (e.g. resume)
|
||||
* @dpms: control display power levels
|
||||
* @save: save CRTC state
|
||||
* @resore: restore CRTC state
|
||||
|
@ -302,6 +303,8 @@ struct drm_crtc_funcs {
|
|||
void (*save)(struct drm_crtc *crtc); /* suspend? */
|
||||
/* Restore CRTC state */
|
||||
void (*restore)(struct drm_crtc *crtc); /* resume? */
|
||||
/* Reset CRTC state */
|
||||
void (*reset)(struct drm_crtc *crtc);
|
||||
|
||||
/* cursor controls */
|
||||
int (*cursor_set)(struct drm_crtc *crtc, struct drm_file *file_priv,
|
||||
|
@ -379,6 +382,7 @@ struct drm_crtc {
|
|||
* @dpms: set power state (see drm_crtc_funcs above)
|
||||
* @save: save connector state
|
||||
* @restore: restore connector state
|
||||
* @reset: reset connector after state has been invalidate (e.g. resume)
|
||||
* @mode_valid: is this mode valid on the given connector?
|
||||
* @mode_fixup: try to fixup proposed mode for this connector
|
||||
* @mode_set: set this mode
|
||||
|
@ -396,6 +400,7 @@ struct drm_connector_funcs {
|
|||
void (*dpms)(struct drm_connector *connector, int mode);
|
||||
void (*save)(struct drm_connector *connector);
|
||||
void (*restore)(struct drm_connector *connector);
|
||||
void (*reset)(struct drm_connector *connector);
|
||||
|
||||
/* Check to see if anything is attached to the connector.
|
||||
* @force is set to false whilst polling, true when checking the
|
||||
|
@ -413,6 +418,7 @@ struct drm_connector_funcs {
|
|||
};
|
||||
|
||||
struct drm_encoder_funcs {
|
||||
void (*reset)(struct drm_encoder *encoder);
|
||||
void (*destroy)(struct drm_encoder *encoder);
|
||||
};
|
||||
|
||||
|
@ -656,6 +662,7 @@ extern struct drm_display_mode *drm_mode_duplicate(struct drm_device *dev,
|
|||
struct drm_display_mode *mode);
|
||||
extern void drm_mode_debug_printmodeline(struct drm_display_mode *mode);
|
||||
extern void drm_mode_config_init(struct drm_device *dev);
|
||||
extern void drm_mode_config_reset(struct drm_device *dev);
|
||||
extern void drm_mode_config_cleanup(struct drm_device *dev);
|
||||
extern void drm_mode_set_name(struct drm_display_mode *mode);
|
||||
extern bool drm_mode_equal(struct drm_display_mode *mode1, struct drm_display_mode *mode2);
|
||||
|
|
|
@ -28,7 +28,6 @@
|
|||
{0x1002, 0x4156, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
|
||||
{0x1002, 0x4237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x4242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
|
||||
{0x1002, 0x4243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
|
||||
{0x1002, 0x4336, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
|
||||
{0x1002, 0x4337, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
|
||||
{0x1002, 0x4437, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
|
||||
|
|
Loading…
Reference in New Issue