powerpc/8xx: remove EXCEPTION_PROLOG/EPILOG_0 and change r3 to r12
EXCEPTION_PROLOG_0 and EXCEPTION_EPILOG_0 were added some time ago in order to regroup the two mtspr/mfspr to SCRATCH0 and SCRATCH1 and the mfcr/mtcr in order to ease entry and exit of function not using the full EXCEPTION_PROLOG. Since then, the mfcr/mtcr has been taken out, hence just leaving the two mtspr/mfspr in the macro. In order to improve readability of the exception functions, we remove those two macros and copy back the two mtspr/mfspr instead. As r10 and r11 are used for SCRATCH0 and SCRATCH1, lets also use r12 for SCRATCH2. It will also improve the readability/maintenance. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Christophe Leroy
Michael Ellerman
parent
2a45addd21
commit
bb9b5a8332
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@ -117,15 +117,12 @@ turn_on_mmu:
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* task's thread_struct.
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*/
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#define EXCEPTION_PROLOG \
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EXCEPTION_PROLOG_0; \
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mtspr SPRN_SPRG_SCRATCH0, r10; \
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mtspr SPRN_SPRG_SCRATCH1, r11; \
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mfcr r10; \
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EXCEPTION_PROLOG_1; \
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EXCEPTION_PROLOG_2
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#define EXCEPTION_PROLOG_0 \
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mtspr SPRN_SPRG_SCRATCH0,r10; \
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mtspr SPRN_SPRG_SCRATCH1,r11
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#define EXCEPTION_PROLOG_1 \
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mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
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andi. r11,r11,MSR_PR; \
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@ -159,13 +156,6 @@ turn_on_mmu:
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SAVE_4GPRS(3, r11); \
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SAVE_2GPRS(7, r11)
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/*
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* Exception exit code.
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*/
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#define EXCEPTION_EPILOG_0 \
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mfspr r10,SPRN_SPRG_SCRATCH0; \
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mfspr r11,SPRN_SPRG_SCRATCH1
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/*
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* Note: code which follows this uses cr0.eq (set if from kernel),
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* r11, r12 (SRR0), and r9 (SRR1).
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@ -309,10 +299,11 @@ SystemCall:
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#endif
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InstructionTLBMiss:
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mtspr SPRN_SPRG_SCRATCH0, r10
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mtspr SPRN_SPRG_SCRATCH1, r11
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#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
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mtspr SPRN_SPRG_SCRATCH2, r3
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mtspr SPRN_SPRG_SCRATCH2, r12
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#endif
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EXCEPTION_PROLOG_0
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#ifdef CONFIG_PPC_8xx_PERF_EVENT
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lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha
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lwz r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
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@ -328,7 +319,7 @@ InstructionTLBMiss:
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/* Only modules will cause ITLB Misses as we always
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* pin the first 8MB of kernel memory */
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#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
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mfcr r3
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mfcr r12
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#endif
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#ifdef ITLB_MISS_KERNEL
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#if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
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@ -371,7 +362,7 @@ _ENTRY(ITLBMiss_cmp)
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lwz r10, 0(r10) /* Get the pte */
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4:
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#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
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mtcr r3
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mtcr r12
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#endif
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/* Insert the APG into the TWC from the Linux PTE. */
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rlwimi r11, r10, 0, 25, 26
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@ -401,10 +392,11 @@ _ENTRY(ITLBMiss_cmp)
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mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
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/* Restore registers */
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mfspr r10, SPRN_SPRG_SCRATCH0
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mfspr r11, SPRN_SPRG_SCRATCH1
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#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
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mfspr r3, SPRN_SPRG_SCRATCH2
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mfspr r12, SPRN_SPRG_SCRATCH2
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#endif
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EXCEPTION_EPILOG_0
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rfi
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#ifdef CONFIG_HUGETLB_PAGE
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@ -434,15 +426,16 @@ _ENTRY(ITLBMiss_cmp)
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. = 0x1200
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DataStoreTLBMiss:
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mtspr SPRN_SPRG_SCRATCH2, r3
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EXCEPTION_PROLOG_0
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mtspr SPRN_SPRG_SCRATCH0, r10
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mtspr SPRN_SPRG_SCRATCH1, r11
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mtspr SPRN_SPRG_SCRATCH2, r12
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#ifdef CONFIG_PPC_8xx_PERF_EVENT
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lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha
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lwz r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
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addi r11, r11, 1
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stw r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
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#endif
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mfcr r3
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mfcr r12
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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@ -482,7 +475,7 @@ _ENTRY(DTLBMiss_jmp)
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rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
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lwz r10, 0(r10) /* Get the pte */
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4:
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mtcr r3
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mtcr r12
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/* Insert the Guarded flag and APG into the TWC from the Linux PTE.
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* It is bit 26-27 of both the Linux PTE and the TWC (at least
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@ -532,9 +525,10 @@ _ENTRY(DTLBMiss_jmp)
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mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
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/* Restore registers */
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mfspr r3, SPRN_SPRG_SCRATCH2
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mtspr SPRN_DAR, r11 /* Tag DAR */
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EXCEPTION_EPILOG_0
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mfspr r10, SPRN_SPRG_SCRATCH0
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mfspr r11, SPRN_SPRG_SCRATCH1
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mfspr r12, SPRN_SPRG_SCRATCH2
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rfi
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#ifdef CONFIG_HUGETLB_PAGE
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@ -584,7 +578,8 @@ itlbie:
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*/
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. = 0x1400
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DataTLBError:
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EXCEPTION_PROLOG_0
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mtspr SPRN_SPRG_SCRATCH0, r10
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mtspr SPRN_SPRG_SCRATCH1, r11
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mfcr r10
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mfspr r11, SPRN_DAR
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@ -619,7 +614,8 @@ dtlbie:
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*/
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. = 0x1c00
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DataBreakpoint:
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EXCEPTION_PROLOG_0
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mtspr SPRN_SPRG_SCRATCH0, r10
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mtspr SPRN_SPRG_SCRATCH1, r11
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mfcr r10
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mfspr r11, SPRN_SRR0
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cmplwi cr0, r11, (dtlbie - PAGE_OFFSET)@l
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@ -635,13 +631,15 @@ DataBreakpoint:
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EXC_XFER_EE(0x1c00, do_break)
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11:
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mtcr r10
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EXCEPTION_EPILOG_0
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mfspr r10, SPRN_SPRG_SCRATCH0
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mfspr r11, SPRN_SPRG_SCRATCH1
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rfi
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#ifdef CONFIG_PPC_8xx_PERF_EVENT
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. = 0x1d00
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InstructionBreakpoint:
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EXCEPTION_PROLOG_0
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mtspr SPRN_SPRG_SCRATCH0, r10
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mtspr SPRN_SPRG_SCRATCH1, r11
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lis r10, (instruction_counter - PAGE_OFFSET)@ha
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lwz r11, (instruction_counter - PAGE_OFFSET)@l(r10)
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addi r11, r11, -1
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@ -649,7 +647,8 @@ InstructionBreakpoint:
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lis r10, 0xffff
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ori r10, r10, 0x01
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mtspr SPRN_COUNTA, r10
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EXCEPTION_EPILOG_0
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mfspr r10, SPRN_SPRG_SCRATCH0
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mfspr r11, SPRN_SPRG_SCRATCH1
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rfi
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#else
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EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
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@ -664,7 +663,7 @@ InstructionBreakpoint:
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* not enough space in the DataStoreTLBMiss area.
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*/
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DTLBMissIMMR:
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mtcr r3
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mtcr r12
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/* Set 512k byte guarded page and mark it valid */
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li r10, MD_PS512K | MD_GUARDED | MD_SVALID
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mtspr SPRN_MD_TWC, r10
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@ -676,12 +675,13 @@ DTLBMissIMMR:
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li r11, RPN_PATTERN
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mtspr SPRN_DAR, r11 /* Tag DAR */
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mfspr r3, SPRN_SPRG_SCRATCH2
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EXCEPTION_EPILOG_0
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mfspr r10, SPRN_SPRG_SCRATCH0
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mfspr r11, SPRN_SPRG_SCRATCH1
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mfspr r12, SPRN_SPRG_SCRATCH2
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rfi
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DTLBMissLinear:
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mtcr r3
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mtcr r12
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/* Set 8M byte page and mark it valid */
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li r11, MD_PS8MEG | MD_SVALID
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mtspr SPRN_MD_TWC, r11
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@ -692,13 +692,14 @@ DTLBMissLinear:
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li r11, RPN_PATTERN
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mtspr SPRN_DAR, r11 /* Tag DAR */
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mfspr r3, SPRN_SPRG_SCRATCH2
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EXCEPTION_EPILOG_0
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mfspr r10, SPRN_SPRG_SCRATCH0
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mfspr r11, SPRN_SPRG_SCRATCH1
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mfspr r12, SPRN_SPRG_SCRATCH2
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rfi
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#ifndef CONFIG_PIN_TLB_TEXT
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ITLBMissLinear:
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mtcr r3
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mtcr r12
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/* Set 8M byte page and mark it valid */
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li r11, MI_PS8MEG | MI_SVALID | _PAGE_EXEC
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mtspr SPRN_MI_TWC, r11
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@ -707,8 +708,9 @@ ITLBMissLinear:
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_PAGE_PRESENT
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mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
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mfspr r3, SPRN_SPRG_SCRATCH2
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EXCEPTION_EPILOG_0
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mfspr r10, SPRN_SPRG_SCRATCH0
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mfspr r11, SPRN_SPRG_SCRATCH1
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mfspr r12, SPRN_SPRG_SCRATCH2
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rfi
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#endif
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