edac: i5100 add 6 ranks per channel
Add support for 6 ranks per channel to the i5100 chipset. I have tested the patch as far as possible with correctible errors and things appear good. The DIMM mapping is correct for our board, but boards may differ. Signed-off-by: Nils Carlson <nils.carlson@ludd.ltu.se> Acked-by: Arthur Jones <ajones@riverbed.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -9,6 +9,11 @@
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* Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
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* http://download.intel.com/design/chipsets/datashts/318378.pdf
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*
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* The intel 5100 has two independent channels. EDAC core currently
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* can not reflect this configuration so instead the chip-select
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* rows for each respective channel are layed out one after another,
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* the first half belonging to channel 0, the second half belonging
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* to channel 1.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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@ -734,7 +739,6 @@ static int i5100_read_spd_byte(const struct mem_ctl_info *mci,
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* fill dimm chip select map
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*
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* FIXME:
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* o only valid for 4 ranks per channel
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* o not the only way to may chip selects to dimm slots
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* o investigate if there is some way to obtain this map from the bios
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*/
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@ -743,8 +747,6 @@ static void __devinit i5100_init_dimm_csmap(struct mem_ctl_info *mci)
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struct i5100_priv *priv = mci->pvt_info;
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int i;
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WARN_ON(priv->ranksperchan != 4);
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for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
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int j;
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@ -753,12 +755,21 @@ static void __devinit i5100_init_dimm_csmap(struct mem_ctl_info *mci)
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}
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/* only 2 chip selects per slot... */
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priv->dimm_csmap[0][0] = 0;
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priv->dimm_csmap[0][1] = 3;
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priv->dimm_csmap[1][0] = 1;
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priv->dimm_csmap[1][1] = 2;
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priv->dimm_csmap[2][0] = 2;
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priv->dimm_csmap[3][0] = 3;
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if (priv->ranksperchan == 4) {
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priv->dimm_csmap[0][0] = 0;
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priv->dimm_csmap[0][1] = 3;
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priv->dimm_csmap[1][0] = 1;
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priv->dimm_csmap[1][1] = 2;
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priv->dimm_csmap[2][0] = 2;
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priv->dimm_csmap[3][0] = 3;
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} else {
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priv->dimm_csmap[0][0] = 0;
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priv->dimm_csmap[0][1] = 1;
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priv->dimm_csmap[1][0] = 2;
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priv->dimm_csmap[1][1] = 3;
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priv->dimm_csmap[2][0] = 4;
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priv->dimm_csmap[2][1] = 5;
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}
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}
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static void __devinit i5100_init_dimm_layout(struct pci_dev *pdev,
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@ -905,13 +916,6 @@ static int __devinit i5100_init_one(struct pci_dev *pdev,
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pci_read_config_dword(pdev, I5100_MS, &dw);
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ranksperch = !!(dw & (1 << 8)) * 2 + 4;
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if (ranksperch != 4) {
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/* FIXME: get 6 ranks / channel to work - need hw... */
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printk(KERN_INFO "i5100_edac: unsupported configuration.\n");
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ret = -ENODEV;
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goto bail_pdev;
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}
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/* enable error reporting... */
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pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw);
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dw &= ~I5100_FERR_NF_MEM_ANY_MASK;
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