firmware: xilinx: Add reset API's
This Patch Adds reset API's to support release, assert and status functionalities by using firmware interface. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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@ -469,6 +469,44 @@ static int zynqmp_pm_ioctl(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2,
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arg1, arg2, out);
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arg1, arg2, out);
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}
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}
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/**
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* zynqmp_pm_reset_assert - Request setting of reset (1 - assert, 0 - release)
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* @reset: Reset to be configured
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* @assert_flag: Flag stating should reset be asserted (1) or
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* released (0)
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*
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* Return: Returns status, either success or error+reason
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*/
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static int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
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const enum zynqmp_pm_reset_action assert_flag)
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{
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return zynqmp_pm_invoke_fn(PM_RESET_ASSERT, reset, assert_flag,
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0, 0, NULL);
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}
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/**
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* zynqmp_pm_reset_get_status - Get status of the reset
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* @reset: Reset whose status should be returned
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* @status: Returned status
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*
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* Return: Returns status, either success or error+reason
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*/
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static int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
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u32 *status)
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{
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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if (!status)
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return -EINVAL;
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ret = zynqmp_pm_invoke_fn(PM_RESET_GET_STATUS, reset, 0,
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0, 0, ret_payload);
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*status = ret_payload[1];
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return ret;
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}
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static const struct zynqmp_eemi_ops eemi_ops = {
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static const struct zynqmp_eemi_ops eemi_ops = {
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.get_api_version = zynqmp_pm_get_api_version,
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.get_api_version = zynqmp_pm_get_api_version,
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.query_data = zynqmp_pm_query_data,
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.query_data = zynqmp_pm_query_data,
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@ -482,6 +520,8 @@ static const struct zynqmp_eemi_ops eemi_ops = {
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.clock_setparent = zynqmp_pm_clock_setparent,
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.clock_setparent = zynqmp_pm_clock_setparent,
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.clock_getparent = zynqmp_pm_clock_getparent,
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.clock_getparent = zynqmp_pm_clock_getparent,
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.ioctl = zynqmp_pm_ioctl,
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.ioctl = zynqmp_pm_ioctl,
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.reset_assert = zynqmp_pm_reset_assert,
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.reset_get_status = zynqmp_pm_reset_get_status,
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};
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};
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/**
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/**
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@ -34,6 +34,8 @@
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enum pm_api_id {
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enum pm_api_id {
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PM_GET_API_VERSION = 1,
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PM_GET_API_VERSION = 1,
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PM_RESET_ASSERT = 17,
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PM_RESET_GET_STATUS,
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PM_IOCTL = 34,
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PM_IOCTL = 34,
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PM_QUERY_DATA,
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PM_QUERY_DATA,
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PM_CLOCK_ENABLE,
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PM_CLOCK_ENABLE,
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@ -75,6 +77,137 @@ enum pm_query_id {
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PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
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PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
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};
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};
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enum zynqmp_pm_reset_action {
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PM_RESET_ACTION_RELEASE,
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PM_RESET_ACTION_ASSERT,
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PM_RESET_ACTION_PULSE,
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};
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enum zynqmp_pm_reset {
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ZYNQMP_PM_RESET_START = 1000,
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ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
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ZYNQMP_PM_RESET_PCIE_BRIDGE,
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ZYNQMP_PM_RESET_PCIE_CTRL,
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ZYNQMP_PM_RESET_DP,
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ZYNQMP_PM_RESET_SWDT_CRF,
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ZYNQMP_PM_RESET_AFI_FM5,
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ZYNQMP_PM_RESET_AFI_FM4,
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ZYNQMP_PM_RESET_AFI_FM3,
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ZYNQMP_PM_RESET_AFI_FM2,
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ZYNQMP_PM_RESET_AFI_FM1,
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ZYNQMP_PM_RESET_AFI_FM0,
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ZYNQMP_PM_RESET_GDMA,
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ZYNQMP_PM_RESET_GPU_PP1,
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ZYNQMP_PM_RESET_GPU_PP0,
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ZYNQMP_PM_RESET_GPU,
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ZYNQMP_PM_RESET_GT,
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ZYNQMP_PM_RESET_SATA,
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ZYNQMP_PM_RESET_ACPU3_PWRON,
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ZYNQMP_PM_RESET_ACPU2_PWRON,
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ZYNQMP_PM_RESET_ACPU1_PWRON,
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ZYNQMP_PM_RESET_ACPU0_PWRON,
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ZYNQMP_PM_RESET_APU_L2,
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ZYNQMP_PM_RESET_ACPU3,
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ZYNQMP_PM_RESET_ACPU2,
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ZYNQMP_PM_RESET_ACPU1,
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ZYNQMP_PM_RESET_ACPU0,
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ZYNQMP_PM_RESET_DDR,
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ZYNQMP_PM_RESET_APM_FPD,
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ZYNQMP_PM_RESET_SOFT,
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ZYNQMP_PM_RESET_GEM0,
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ZYNQMP_PM_RESET_GEM1,
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ZYNQMP_PM_RESET_GEM2,
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ZYNQMP_PM_RESET_GEM3,
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ZYNQMP_PM_RESET_QSPI,
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ZYNQMP_PM_RESET_UART0,
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ZYNQMP_PM_RESET_UART1,
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ZYNQMP_PM_RESET_SPI0,
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ZYNQMP_PM_RESET_SPI1,
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ZYNQMP_PM_RESET_SDIO0,
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ZYNQMP_PM_RESET_SDIO1,
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ZYNQMP_PM_RESET_CAN0,
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ZYNQMP_PM_RESET_CAN1,
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ZYNQMP_PM_RESET_I2C0,
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ZYNQMP_PM_RESET_I2C1,
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ZYNQMP_PM_RESET_TTC0,
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ZYNQMP_PM_RESET_TTC1,
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ZYNQMP_PM_RESET_TTC2,
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ZYNQMP_PM_RESET_TTC3,
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ZYNQMP_PM_RESET_SWDT_CRL,
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ZYNQMP_PM_RESET_NAND,
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ZYNQMP_PM_RESET_ADMA,
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ZYNQMP_PM_RESET_GPIO,
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ZYNQMP_PM_RESET_IOU_CC,
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ZYNQMP_PM_RESET_TIMESTAMP,
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ZYNQMP_PM_RESET_RPU_R50,
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ZYNQMP_PM_RESET_RPU_R51,
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ZYNQMP_PM_RESET_RPU_AMBA,
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ZYNQMP_PM_RESET_OCM,
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ZYNQMP_PM_RESET_RPU_PGE,
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ZYNQMP_PM_RESET_USB0_CORERESET,
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ZYNQMP_PM_RESET_USB1_CORERESET,
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ZYNQMP_PM_RESET_USB0_HIBERRESET,
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ZYNQMP_PM_RESET_USB1_HIBERRESET,
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ZYNQMP_PM_RESET_USB0_APB,
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ZYNQMP_PM_RESET_USB1_APB,
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ZYNQMP_PM_RESET_IPI,
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ZYNQMP_PM_RESET_APM_LPD,
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ZYNQMP_PM_RESET_RTC,
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ZYNQMP_PM_RESET_SYSMON,
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ZYNQMP_PM_RESET_AFI_FM6,
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ZYNQMP_PM_RESET_LPD_SWDT,
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ZYNQMP_PM_RESET_FPD,
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ZYNQMP_PM_RESET_RPU_DBG1,
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ZYNQMP_PM_RESET_RPU_DBG0,
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ZYNQMP_PM_RESET_DBG_LPD,
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ZYNQMP_PM_RESET_DBG_FPD,
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ZYNQMP_PM_RESET_APLL,
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ZYNQMP_PM_RESET_DPLL,
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ZYNQMP_PM_RESET_VPLL,
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ZYNQMP_PM_RESET_IOPLL,
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ZYNQMP_PM_RESET_RPLL,
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ZYNQMP_PM_RESET_GPO3_PL_0,
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ZYNQMP_PM_RESET_GPO3_PL_1,
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ZYNQMP_PM_RESET_GPO3_PL_2,
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ZYNQMP_PM_RESET_GPO3_PL_3,
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ZYNQMP_PM_RESET_GPO3_PL_4,
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ZYNQMP_PM_RESET_GPO3_PL_5,
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ZYNQMP_PM_RESET_GPO3_PL_6,
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ZYNQMP_PM_RESET_GPO3_PL_7,
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ZYNQMP_PM_RESET_GPO3_PL_8,
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ZYNQMP_PM_RESET_GPO3_PL_9,
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ZYNQMP_PM_RESET_GPO3_PL_10,
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ZYNQMP_PM_RESET_GPO3_PL_11,
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ZYNQMP_PM_RESET_GPO3_PL_12,
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ZYNQMP_PM_RESET_GPO3_PL_13,
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ZYNQMP_PM_RESET_GPO3_PL_14,
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ZYNQMP_PM_RESET_GPO3_PL_15,
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ZYNQMP_PM_RESET_GPO3_PL_16,
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ZYNQMP_PM_RESET_GPO3_PL_17,
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ZYNQMP_PM_RESET_GPO3_PL_18,
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ZYNQMP_PM_RESET_GPO3_PL_19,
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ZYNQMP_PM_RESET_GPO3_PL_20,
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ZYNQMP_PM_RESET_GPO3_PL_21,
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ZYNQMP_PM_RESET_GPO3_PL_22,
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ZYNQMP_PM_RESET_GPO3_PL_23,
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ZYNQMP_PM_RESET_GPO3_PL_24,
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ZYNQMP_PM_RESET_GPO3_PL_25,
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ZYNQMP_PM_RESET_GPO3_PL_26,
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ZYNQMP_PM_RESET_GPO3_PL_27,
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ZYNQMP_PM_RESET_GPO3_PL_28,
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ZYNQMP_PM_RESET_GPO3_PL_29,
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ZYNQMP_PM_RESET_GPO3_PL_30,
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ZYNQMP_PM_RESET_GPO3_PL_31,
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ZYNQMP_PM_RESET_RPU_LS,
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ZYNQMP_PM_RESET_PS_ONLY,
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ZYNQMP_PM_RESET_PL,
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ZYNQMP_PM_RESET_PS_PL0,
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ZYNQMP_PM_RESET_PS_PL1,
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ZYNQMP_PM_RESET_PS_PL2,
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ZYNQMP_PM_RESET_PS_PL3,
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ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
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};
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/**
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/**
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* struct zynqmp_pm_query_data - PM query data
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* struct zynqmp_pm_query_data - PM query data
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* @qid: query ID
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* @qid: query ID
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@ -102,6 +235,9 @@ struct zynqmp_eemi_ops {
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int (*clock_setparent)(u32 clock_id, u32 parent_id);
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int (*clock_setparent)(u32 clock_id, u32 parent_id);
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int (*clock_getparent)(u32 clock_id, u32 *parent_id);
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int (*clock_getparent)(u32 clock_id, u32 *parent_id);
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int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
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int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
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int (*reset_assert)(const enum zynqmp_pm_reset reset,
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const enum zynqmp_pm_reset_action assert_flag);
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int (*reset_get_status)(const enum zynqmp_pm_reset reset, u32 *status);
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};
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};
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#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
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#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
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