Merge branch 'queue/irq/gpio' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip into devel
This commit is contained in:
commit
bcae888039
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@ -438,7 +438,7 @@ static void bcm_kona_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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void __iomem *reg_base;
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int bit, bank_id;
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unsigned long sta;
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struct bcm_kona_gpio_bank *bank = irq_get_handler_data(irq);
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struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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chained_irq_enter(chip, desc);
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@ -65,11 +65,11 @@ static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
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return ptr;
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}
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static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
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static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
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{
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struct davinci_gpio_regs __iomem *g;
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g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
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g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
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return g;
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}
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@ -287,7 +287,7 @@ static int davinci_gpio_probe(struct platform_device *pdev)
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static void gpio_irq_disable(struct irq_data *d)
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{
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struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
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struct davinci_gpio_regs __iomem *g = irq2regs(d);
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u32 mask = (u32) irq_data_get_irq_handler_data(d);
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writel_relaxed(mask, &g->clr_falling);
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@ -296,7 +296,7 @@ static void gpio_irq_disable(struct irq_data *d)
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static void gpio_irq_enable(struct irq_data *d)
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{
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struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
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struct davinci_gpio_regs __iomem *g = irq2regs(d);
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u32 mask = (u32) irq_data_get_irq_handler_data(d);
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unsigned status = irqd_get_trigger_type(d);
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@ -327,8 +327,9 @@ static struct irq_chip gpio_irqchip = {
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};
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static void
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gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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gpio_irq_handler(unsigned __irq, struct irq_desc *desc)
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{
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unsigned int irq = irq_desc_get_irq(desc);
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struct davinci_gpio_regs __iomem *g;
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u32 mask = 0xffff;
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struct davinci_gpio_controller *d;
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@ -396,7 +397,7 @@ static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
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struct davinci_gpio_regs __iomem *g;
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u32 mask;
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d = (struct davinci_gpio_controller *)data->handler_data;
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d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
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g = (struct davinci_gpio_regs __iomem *)d->regs;
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mask = __gpio_mask(data->irq - d->gpio_irq);
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@ -578,15 +579,13 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
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writel_relaxed(~0, &g->clr_falling);
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writel_relaxed(~0, &g->clr_rising);
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/* set up all irqs in this bank */
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irq_set_chained_handler(bank_irq, gpio_irq_handler);
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/*
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* Each chip handles 32 gpios, and each irq bank consists of 16
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* gpio irqs. Pass the irq bank's corresponding controller to
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* the chained irq handler.
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*/
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irq_set_handler_data(bank_irq, &chips[gpio / 32]);
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irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler,
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&chips[gpio / 32]);
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binten |= BIT(bank);
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}
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@ -149,7 +149,7 @@ static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
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static void dwapb_irq_handler(u32 irq, struct irq_desc *desc)
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{
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struct dwapb_gpio *gpio = irq_get_handler_data(irq);
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struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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dwapb_do_irq(gpio);
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@ -100,13 +100,15 @@ static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
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}
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}
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static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
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static void ep93xx_gpio_f_irq_handler(unsigned int __irq,
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struct irq_desc *desc)
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{
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/*
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* map discontiguous hw irq range to continuous sw irq range:
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*
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* IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
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*/
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unsigned int irq = irq_desc_get_irq(desc);
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int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
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int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
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@ -208,7 +210,7 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
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return -EINVAL;
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}
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__irq_set_handler_locked(d->irq, handler);
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irq_set_handler_locked(d, handler);
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gpio_int_enabled[port] |= port_mask;
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@ -396,8 +396,8 @@ static int mpc8xxx_probe(struct platform_device *pdev)
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out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
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out_be32(mm_gc->regs + GPIO_IMR, 0);
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irq_set_handler_data(mpc8xxx_gc->irqn, mpc8xxx_gc);
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irq_set_chained_handler(mpc8xxx_gc->irqn, mpc8xxx_gpio_irq_cascade);
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irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
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mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
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return 0;
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}
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@ -407,8 +407,7 @@ static int mpc8xxx_remove(struct platform_device *pdev)
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
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if (mpc8xxx_gc->irq) {
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irq_set_handler_data(mpc8xxx_gc->irqn, NULL);
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irq_set_chained_handler(mpc8xxx_gc->irqn, NULL);
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irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
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irq_domain_remove(mpc8xxx_gc->irq);
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}
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@ -187,14 +187,6 @@ static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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return irq_create_mapping(domain, offset);
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}
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static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq)
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{
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struct irq_data *irq_data = irq_get_irq_data(irq);
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return irq_data->hwirq;
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}
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/* For dual-edge interrupts in software, since the hardware has no
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* such support:
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*
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@ -238,7 +230,7 @@ static void msm_gpio_update_dual_edge_pos(unsigned gpio)
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static void msm_gpio_irq_ack(struct irq_data *d)
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{
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int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
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int gpio = d->hwirq;
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writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio));
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if (test_bit(gpio, msm_gpio.dual_edge_irqs))
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@ -247,8 +239,8 @@ static void msm_gpio_irq_ack(struct irq_data *d)
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static void msm_gpio_irq_mask(struct irq_data *d)
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{
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int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
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unsigned long irq_flags;
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int gpio = d->hwirq;
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spin_lock_irqsave(&tlmm_lock, irq_flags);
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writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio));
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@ -259,8 +251,8 @@ static void msm_gpio_irq_mask(struct irq_data *d)
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static void msm_gpio_irq_unmask(struct irq_data *d)
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{
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int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
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unsigned long irq_flags;
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int gpio = d->hwirq;
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spin_lock_irqsave(&tlmm_lock, irq_flags);
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__set_bit(gpio, msm_gpio.enabled_irqs);
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@ -271,8 +263,8 @@ static void msm_gpio_irq_unmask(struct irq_data *d)
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static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
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unsigned long irq_flags;
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int gpio = d->hwirq;
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uint32_t bits;
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spin_lock_irqsave(&tlmm_lock, irq_flags);
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@ -281,14 +273,14 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
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if (flow_type & IRQ_TYPE_EDGE_BOTH) {
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bits |= BIT(INTR_DECT_CTL);
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__irq_set_handler_locked(d->irq, handle_edge_irq);
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irq_set_handler_locked(d, handle_edge_irq);
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if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
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__set_bit(gpio, msm_gpio.dual_edge_irqs);
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else
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__clear_bit(gpio, msm_gpio.dual_edge_irqs);
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} else {
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bits &= ~BIT(INTR_DECT_CTL);
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__irq_set_handler_locked(d->irq, handle_level_irq);
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irq_set_handler_locked(d, handle_level_irq);
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__clear_bit(gpio, msm_gpio.dual_edge_irqs);
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}
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@ -331,7 +323,7 @@ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
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static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
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int gpio = d->hwirq;
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if (on) {
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if (bitmap_empty(msm_gpio.wake_irqs, MAX_NR_GPIO))
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@ -458,9 +458,9 @@ static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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return 0;
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}
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static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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static void mvebu_gpio_irq_handler(unsigned int __irq, struct irq_desc *desc)
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{
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struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq);
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struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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u32 cause, type;
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int i;
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@ -787,8 +787,8 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
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if (irq < 0)
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continue;
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irq_set_handler_data(irq, mvchip);
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irq_set_chained_handler(irq, mvebu_gpio_irq_handler);
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irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
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mvchip);
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}
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mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
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@ -275,8 +275,8 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
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static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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{
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u32 irq_stat;
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struct mxc_gpio_port *port = irq_get_handler_data(irq);
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struct irq_chip *chip = irq_get_chip(irq);
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struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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chained_irq_enter(chip, desc);
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@ -292,7 +292,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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{
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u32 irq_msk, irq_stat;
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struct mxc_gpio_port *port;
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struct irq_chip *chip = irq_get_chip(irq);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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chained_irq_enter(chip, desc);
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@ -157,7 +157,7 @@ static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
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static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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{
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u32 irq_stat;
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struct mxs_gpio_port *port = irq_get_handler_data(irq);
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struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
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desc->irq_data.chip->irq_ack(&desc->irq_data);
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@ -511,9 +511,9 @@ static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
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spin_unlock_irqrestore(&bank->lock, flags);
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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__irq_set_handler_locked(d->irq, handle_level_irq);
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irq_set_handler_locked(d, handle_level_irq);
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else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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__irq_set_handler_locked(d->irq, handle_edge_irq);
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irq_set_handler_locked(d, handle_edge_irq);
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return 0;
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@ -714,7 +714,7 @@ static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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struct gpio_bank *bank;
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int unmasked = 0;
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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struct gpio_chip *chip = irq_get_handler_data(irq);
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struct gpio_chip *chip = irq_desc_get_handler_data(desc);
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chained_irq_enter(irqchip, desc);
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@ -281,9 +281,9 @@ static int pch_irq_type(struct irq_data *d, unsigned int type)
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/* And the handler */
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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__irq_set_handler_locked(d->irq, handle_level_irq);
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irq_set_handler_locked(d, handle_level_irq);
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else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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__irq_set_handler_locked(d->irq, handle_edge_irq);
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irq_set_handler_locked(d, handle_edge_irq);
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unlock:
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spin_unlock_irqrestore(&chip->spinlock, flags);
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|
|
|
@ -173,9 +173,9 @@ static struct irq_domain *sa1100_gpio_irqdomain;
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* and call the handler.
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*/
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static void
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sa1100_gpio_handler(unsigned int irq, struct irq_desc *desc)
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sa1100_gpio_handler(unsigned int __irq, struct irq_desc *desc)
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{
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unsigned int mask;
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unsigned int irq, mask;
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mask = GEDR;
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do {
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|
|
|
@ -252,9 +252,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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tegra_gpio_enable(gpio);
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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__irq_set_handler_locked(d->irq, handle_level_irq);
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irq_set_handler_locked(d, handle_level_irq);
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else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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__irq_set_handler_locked(d->irq, handle_edge_irq);
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irq_set_handler_locked(d, handle_edge_irq);
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return 0;
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}
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|
@ -268,16 +268,14 @@ static void tegra_gpio_irq_shutdown(struct irq_data *d)
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|
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static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
|
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struct tegra_gpio_bank *bank;
|
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int port;
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int pin;
|
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int unmasked = 0;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
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chained_irq_enter(chip, desc);
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bank = irq_get_handler_data(irq);
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|
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for (port = 0; port < 4; port++) {
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int gpio = tegra_gpio_compose(bank->bank, port, 0);
|
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unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
|
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|
|
|
@ -194,11 +194,12 @@ out:
|
|||
|
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static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
|
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{
|
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struct timbgpio *tgpio = irq_get_handler_data(irq);
|
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struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
|
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struct irq_data *data = irq_desc_get_irq_data(desc);
|
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unsigned long ipr;
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int offset;
|
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|
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desc->irq_data.chip->irq_ack(irq_get_irq_data(irq));
|
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data->chip->irq_ack(data);
|
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ipr = ioread32(tgpio->membase + TGPIO_IPR);
|
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iowrite32(ipr, tgpio->membase + TGPIO_ICR);
|
||||
|
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|
@ -299,8 +300,7 @@ static int timbgpio_probe(struct platform_device *pdev)
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#endif
|
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}
|
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|
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irq_set_handler_data(irq, tgpio);
|
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irq_set_chained_handler(irq, timbgpio_irq);
|
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irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio);
|
||||
|
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return 0;
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}
|
||||
|
|
|
@ -510,8 +510,8 @@ static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info)
|
|||
gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
|
||||
|
||||
/* Setup chained handler for this GPIO bank */
|
||||
irq_set_handler_data(bank->irq, bank);
|
||||
irq_set_chained_handler(bank->irq, tz1090_gpio_irq_handler);
|
||||
irq_set_chained_handler_and_data(bank->irq, tz1090_gpio_irq_handler,
|
||||
bank);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -120,7 +120,7 @@ static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
|
|||
|
||||
static void vf610_gpio_irq_handler(u32 irq, struct irq_desc *desc)
|
||||
{
|
||||
struct vf610_gpio_port *port = irq_get_handler_data(irq);
|
||||
struct vf610_gpio_port *port = irq_desc_get_handler_data(desc);
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
int pin;
|
||||
unsigned long irq_isfr;
|
||||
|
|
|
@ -441,10 +441,10 @@ static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
|
|||
gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
|
||||
|
||||
if (type & IRQ_TYPE_LEVEL_MASK) {
|
||||
__irq_set_chip_handler_name_locked(irq_data->irq,
|
||||
irq_set_chip_handler_name_locked(irq_data,
|
||||
&zynq_gpio_level_irqchip, handle_fasteoi_irq, NULL);
|
||||
} else {
|
||||
__irq_set_chip_handler_name_locked(irq_data->irq,
|
||||
irq_set_chip_handler_name_locked(irq_data,
|
||||
&zynq_gpio_edge_irqchip, handle_level_irq, NULL);
|
||||
}
|
||||
|
||||
|
@ -518,7 +518,7 @@ static void zynq_gpio_irqhandler(unsigned int irq, struct irq_desc *desc)
|
|||
{
|
||||
u32 int_sts, int_enb;
|
||||
unsigned int bank_num;
|
||||
struct zynq_gpio *gpio = irq_get_handler_data(irq);
|
||||
struct zynq_gpio *gpio = irq_desc_get_handler_data(desc);
|
||||
struct irq_chip *irqchip = irq_desc_get_chip(desc);
|
||||
|
||||
chained_irq_enter(irqchip, desc);
|
||||
|
|
|
@ -446,8 +446,8 @@ void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
|
|||
* The parent irqchip is already using the chip_data for this
|
||||
* irqchip, so our callbacks simply use the handler_data.
|
||||
*/
|
||||
irq_set_handler_data(parent_irq, gpiochip);
|
||||
irq_set_chained_handler(parent_irq, parent_handler);
|
||||
irq_set_chained_handler_and_data(parent_irq, parent_handler,
|
||||
gpiochip);
|
||||
|
||||
gpiochip->irq_parent = parent_irq;
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue