ARM: shmobile: r8a7790: add MSTP10 support on DTSI
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -835,6 +835,39 @@
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"rcan1", "rcan0", "qspi_mod", "iic3",
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"i2c3", "i2c2", "i2c1", "i2c0";
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};
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mstp10_clks: mstp10_clks@e6150998 {
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
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clocks = <&p_clk>,
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<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
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<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
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<&p_clk>,
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<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
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<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
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<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
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<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
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<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
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<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
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#clock-cells = <1>;
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clock-indices = <
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R8A7790_CLK_SSI_ALL
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R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
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R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
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R8A7790_CLK_SCU_ALL
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R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
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R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
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R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
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>;
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clock-output-names =
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"ssi-all",
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"ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
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"ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
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"scu-all",
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"scu-dvc1", "scu-dvc0",
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"scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
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"scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
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};
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};
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qspi: spi@e6b10000 {
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@ -107,4 +107,30 @@
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#define R8A7790_CLK_I2C1 30
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#define R8A7790_CLK_I2C0 31
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/* MSTP10 */
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#define R8A7790_CLK_SSI_ALL 5
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#define R8A7790_CLK_SSI9 6
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#define R8A7790_CLK_SSI8 7
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#define R8A7790_CLK_SSI7 8
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#define R8A7790_CLK_SSI6 9
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#define R8A7790_CLK_SSI5 10
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#define R8A7790_CLK_SSI4 11
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#define R8A7790_CLK_SSI3 12
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#define R8A7790_CLK_SSI2 13
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#define R8A7790_CLK_SSI1 14
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#define R8A7790_CLK_SSI0 15
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#define R8A7790_CLK_SCU_ALL 17
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#define R8A7790_CLK_SCU_DVC1 18
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#define R8A7790_CLK_SCU_DVC0 19
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#define R8A7790_CLK_SCU_SRC9 22
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#define R8A7790_CLK_SCU_SRC8 23
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#define R8A7790_CLK_SCU_SRC7 24
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#define R8A7790_CLK_SCU_SRC6 25
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#define R8A7790_CLK_SCU_SRC5 26
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#define R8A7790_CLK_SCU_SRC4 27
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#define R8A7790_CLK_SCU_SRC3 28
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#define R8A7790_CLK_SCU_SRC2 29
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#define R8A7790_CLK_SCU_SRC1 30
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#define R8A7790_CLK_SCU_SRC0 31
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#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
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