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ARM: dts: sun8i: Move A23/A33 usbphy and usb_otg nodes to common dtsi 

The usbphy and usb_otg nodes in the A23 and A33 dts files only differ
by compatible, and for the usbphy, the size of one of its register
regions.

Move all the common bits to the A23/A33 common dtsi file.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Chen-Yu Tsai 2016-09-08 11:25:35 +08:00 committed by Maxime Ripard
parent 3353bedc4d
commit bd33544e25
3 changed files with 50 additions and 64 deletions
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30
arch/arm/boot/dts/sun8i-a23-a33.dtsi
View File

@ -202,6 +202,36 @@
#size-cells = <0>;
};
usb_otg: usb@01c19000 {
/* compatible gets set in SoC specific dtsi file */
reg = <0x01c19000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
status = "disabled";
};
usbphy: phy@01c19400 {
/*
* compatible and address regions get set in
* SoC specific dtsi file
*/
clocks = <&ccu CLK_USB_PHY0>,
<&ccu CLK_USB_PHY1>;
clock-names = "usb0_phy",
"usb1_phy";
resets = <&ccu RST_USB_PHY0>,
<&ccu RST_USB_PHY1>;
reset-names = "usb0_reset",
"usb1_reset";
status = "disabled";
#phy-cells = <1>;
};
ehci0: usb@01c1a000 {
compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
reg = <0x01c1a000 0x100>;

43
arch/arm/boot/dts/sun8i-a23.dtsi
View File

@ -48,39 +48,6 @@
memory {
reg = <0x40000000 0x40000000>;
};
soc@01c00000 {
usb_otg: usb@01c19000 {
compatible = "allwinner,sun6i-a31-musb";
reg = <0x01c19000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
status = "disabled";
};
usbphy: phy@01c19400 {
compatible = "allwinner,sun8i-a23-usb-phy";
reg = <0x01c19400 0x10>,
<0x01c1a800 0x4>;
reg-names = "phy_ctrl",
"pmu1";
clocks = <&ccu CLK_USB_PHY0>,
<&ccu CLK_USB_PHY1>;
clock-names = "usb0_phy",
"usb1_phy";
resets = <&ccu RST_USB_PHY0>,
<&ccu RST_USB_PHY1>;
reset-names = "usb0_reset",
"usb1_reset";
status = "disabled";
#phy-cells = <1>;
};
};
};
&ccu {
@ -93,3 +60,13 @@
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
};
&usb_otg {
compatible = "allwinner,sun6i-a31-musb";
};
&usbphy {
compatible = "allwinner,sun8i-a23-usb-phy";
reg = <0x01c19400 0x10>, <0x01c1a800 0x4>;
reg-names = "phy_ctrl", "pmu1";
};

41
arch/arm/boot/dts/sun8i-a33.dtsi
View File

@ -116,37 +116,6 @@
reset-names = "ahb";
};
usb_otg: usb@01c19000 {
compatible = "allwinner,sun8i-a33-musb";
reg = <0x01c19000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
status = "disabled";
};
usbphy: phy@01c19400 {
compatible = "allwinner,sun8i-a33-usb-phy";
reg = <0x01c19400 0x14>,
<0x01c1a800 0x4>;
reg-names = "phy_ctrl",
"pmu1";
clocks = <&ccu CLK_USB_PHY0>,
<&ccu CLK_USB_PHY1>;
clock-names = "usb0_phy",
"usb1_phy";
resets = <&ccu RST_USB_PHY0>,
<&ccu RST_USB_PHY1>;
reset-names = "usb0_reset",
"usb1_reset";
status = "disabled";
#phy-cells = <1>;
};
fe0: display-frontend@01e00000 {
compatible = "allwinner,sun8i-a33-display-frontend";
reg = <0x01e00000 0x20000>;
@ -276,3 +245,13 @@
};
};
&usb_otg {
compatible = "allwinner,sun8i-a33-musb";
};
&usbphy {
compatible = "allwinner,sun8i-a33-usb-phy";
reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
reg-names = "phy_ctrl", "pmu1";
};