drm/dp: indentation and ordering cleanups
Keep the DPCD macros ordered by address, and make indentation conform to
the rest of the file.
commit e045d20bef
Author: Sonika Jindal <sonika.jindal@intel.com>
Date: Thu Feb 19 13:16:44 2015 +0530
drm: Adding edp1.4 specific dpcd macros
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
parent
2e3afd47ab
commit
bd5da992b9
|
@ -92,9 +92,6 @@
|
||||||
# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
|
# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
|
||||||
# define DP_OUI_SUPPORT (1 << 7)
|
# define DP_OUI_SUPPORT (1 << 7)
|
||||||
|
|
||||||
#define DP_SUPPORTED_LINK_RATES 0x010 /*eDP 1.4*/
|
|
||||||
#define DP_MAX_SUPPORTED_RATES 0x8
|
|
||||||
|
|
||||||
#define DP_I2C_SPEED_CAP 0x00c /* DPI */
|
#define DP_I2C_SPEED_CAP 0x00c /* DPI */
|
||||||
# define DP_I2C_SPEED_1K 0x01
|
# define DP_I2C_SPEED_1K 0x01
|
||||||
# define DP_I2C_SPEED_5K 0x02
|
# define DP_I2C_SPEED_5K 0x02
|
||||||
|
@ -105,8 +102,12 @@
|
||||||
|
|
||||||
#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
|
#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
|
||||||
# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
|
# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
|
||||||
|
|
||||||
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
|
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
|
||||||
|
|
||||||
|
#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
|
||||||
|
# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
|
||||||
|
|
||||||
/* Multiple stream transport */
|
/* Multiple stream transport */
|
||||||
#define DP_FAUX_CAP 0x020 /* 1.2 */
|
#define DP_FAUX_CAP 0x020 /* 1.2 */
|
||||||
# define DP_FAUX_CAP_1 (1 << 0)
|
# define DP_FAUX_CAP_1 (1 << 0)
|
||||||
|
@ -225,7 +226,7 @@
|
||||||
# define DP_UP_REQ_EN (1 << 1)
|
# define DP_UP_REQ_EN (1 << 1)
|
||||||
# define DP_UPSTREAM_IS_SRC (1 << 2)
|
# define DP_UPSTREAM_IS_SRC (1 << 2)
|
||||||
|
|
||||||
#define DP_LINK_RATE_SET 0x115
|
#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
|
||||||
|
|
||||||
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
|
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
|
||||||
# define DP_PSR_ENABLE (1 << 0)
|
# define DP_PSR_ENABLE (1 << 0)
|
||||||
|
@ -338,7 +339,7 @@
|
||||||
# define DP_SET_POWER_D3 0x2
|
# define DP_SET_POWER_D3 0x2
|
||||||
# define DP_SET_POWER_MASK 0x3
|
# define DP_SET_POWER_MASK 0x3
|
||||||
|
|
||||||
#define DP_EDP_DPCD_REV 0x700
|
#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
|
||||||
|
|
||||||
#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
|
#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
|
||||||
#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
|
#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
|
||||||
|
|
Loading…
Reference in New Issue