From bd6f27458b0c50469ba1bb0a53e5ad1ac9e950d5 Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Tue, 10 Dec 2013 09:25:47 -0300 Subject: [PATCH] [media] v4l: atmel-isi: Should clear bits before set the hardware register In the ISI driver it reads the config register to get original value, then set the correct FRATE_DIV and YCC_SWAP_MODE directly. This will cause some bits overlap. So we need to clear these bits first, then set correct value. This patch fix it. Signed-off-by: Josh Wu Acked-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/soc_camera/atmel-isi.c | 3 +++ include/media/atmel-isi.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/media/platform/soc_camera/atmel-isi.c b/drivers/media/platform/soc_camera/atmel-isi.c index 9c4cadc4de38..4835173d7f80 100644 --- a/drivers/media/platform/soc_camera/atmel-isi.c +++ b/drivers/media/platform/soc_camera/atmel-isi.c @@ -132,6 +132,8 @@ static int configure_geometry(struct atmel_isi *isi, u32 width, isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS); cfg2 = isi_readl(isi, ISI_CFG2); + /* Set YCC swap mode */ + cfg2 &= ~ISI_CFG2_YCC_SWAP_MODE_MASK; cfg2 |= cr; /* Set width */ cfg2 &= ~(ISI_CFG2_IM_HSIZE_MASK); @@ -346,6 +348,7 @@ static void start_dma(struct atmel_isi *isi, struct frame_buffer *buffer) isi_writel(isi, ISI_DMA_C_CTRL, ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE); isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_C_CH); + cfg1 &= ~ISI_CFG1_FRATE_DIV_MASK; /* Enable linked list */ cfg1 |= isi->pdata->frate | ISI_CFG1_DISCR; diff --git a/include/media/atmel-isi.h b/include/media/atmel-isi.h index 656823075709..2b023471ac89 100644 --- a/include/media/atmel-isi.h +++ b/include/media/atmel-isi.h @@ -56,6 +56,7 @@ #define ISI_CFG1_FRATE_DIV_6 (5 << 8) #define ISI_CFG1_FRATE_DIV_7 (6 << 8) #define ISI_CFG1_FRATE_DIV_8 (7 << 8) +#define ISI_CFG1_FRATE_DIV_MASK (7 << 8) #define ISI_CFG1_DISCR (1 << 11) #define ISI_CFG1_FULL_MODE (1 << 12) @@ -66,6 +67,7 @@ #define ISI_CFG2_YCC_SWAP_MODE_1 (1 << 28) #define ISI_CFG2_YCC_SWAP_MODE_2 (2 << 28) #define ISI_CFG2_YCC_SWAP_MODE_3 (3 << 28) +#define ISI_CFG2_YCC_SWAP_MODE_MASK (3 << 28) #define ISI_CFG2_IM_VSIZE_OFFSET 0 #define ISI_CFG2_IM_HSIZE_OFFSET 16 #define ISI_CFG2_IM_VSIZE_MASK (0x7FF << ISI_CFG2_IM_VSIZE_OFFSET)