clk: tegra: Add CEC clock

This clock is used to clock the HDMI CEC interface.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Peter De Schrijver 2017-02-28 16:37:17 +02:00 committed by Thierry Reding
parent e589376dab
commit bfa34832df
10 changed files with 10 additions and 4 deletions

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@ -308,6 +308,7 @@ enum clk_id {
tegra_clk_sclk_mux,
tegra_clk_sor_safe,
tegra_clk_ispa,
tegra_clk_cec,
tegra_clk_max,
};

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@ -837,6 +837,7 @@ static struct tegra_periph_init_data gate_clks[] = {
GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0),
GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),
GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0),
GATE("cec", "pclk", 136, 0, tegra_clk_cec, 0),
};
static struct tegra_periph_init_data div_clks[] = {

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@ -819,6 +819,7 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
[tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
[tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
[tegra_clk_cec] = { .dt_id = TEGRA114_CLK_CEC, .present = true },
};
static struct tegra_devclk devclks[] __initdata = {

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@ -928,6 +928,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
[tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true },
};
static struct tegra_devclk devclks[] __initdata = {

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@ -2222,6 +2222,7 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
[tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
[tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },
[tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true },
[tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true },
};
static struct tegra_devclk devclks[] __initdata = {

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@ -817,6 +817,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
[tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
[tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
[tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
[tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true },
};
static const char *pll_e_parents[] = { "pll_ref", "pll_p" };

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@ -156,7 +156,7 @@
/* 133 */
/* 134 */
/* 135 */
/* 136 */
#define TEGRA114_CLK_CEC 136
/* 137 */
/* 138 */
/* 139 */

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@ -156,7 +156,7 @@
/* 133 */
/* 134 */
/* 135 */
/* 136 */
#define TEGRA124_CLK_CEC 136
/* 137 */
/* 138 */
/* 139 */

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@ -156,7 +156,7 @@
/* 133 */
/* 134 */
/* 135 */
/* 136 */
#define TEGRA210_CLK_CEC 136
/* 137 */
/* 138 */
/* 139 */

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@ -156,7 +156,7 @@
/* 133 */
/* 134 */
/* 135 */
/* 136 */
#define TEGRA30_CLK_CEC 136
/* 137 */
/* 138 */
/* 139 */