x86: HPET force enable for ICH5
force_enable hpet for ICH5. [ Build fixes from Andrew Morton ] Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: john stultz <johnstul@us.ibm.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Arjan van de Ven <arjan@linux.intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@ -181,7 +181,7 @@ static void hpet_start_counter(void)
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static void hpet_resume_device(void)
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static void hpet_resume_device(void)
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{
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{
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ich_force_hpet_resume();
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force_hpet_resume();
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}
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}
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static void hpet_restart_counter(void)
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static void hpet_restart_counter(void)
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@ -53,9 +53,15 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quir
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#if defined(CONFIG_HPET_TIMER)
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#if defined(CONFIG_HPET_TIMER)
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unsigned long force_hpet_address;
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unsigned long force_hpet_address;
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static enum {
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NONE_FORCE_HPET_RESUME,
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OLD_ICH_FORCE_HPET_RESUME,
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ICH_FORCE_HPET_RESUME
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} force_hpet_resume_type;
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static void __iomem *rcba_base;
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static void __iomem *rcba_base;
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void ich_force_hpet_resume(void)
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static void ich_force_hpet_resume(void)
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{
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{
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u32 val;
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u32 val;
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@ -133,6 +139,7 @@ static void ich_force_enable_hpet(struct pci_dev *dev)
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iounmap(rcba_base);
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iounmap(rcba_base);
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printk(KERN_DEBUG "Failed to force enable HPET\n");
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printk(KERN_DEBUG "Failed to force enable HPET\n");
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} else {
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} else {
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force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
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printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
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printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
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force_hpet_address);
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force_hpet_address);
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}
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}
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@ -148,4 +155,98 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
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ich_force_enable_hpet);
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ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
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ich_force_enable_hpet);
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ich_force_enable_hpet);
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static struct pci_dev *cached_dev;
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static void old_ich_force_hpet_resume(void)
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{
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u32 val;
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u32 uninitialized_var(gen_cntl);
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if (!force_hpet_address || !cached_dev)
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return;
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pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
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gen_cntl &= (~(0x7 << 15));
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gen_cntl |= (0x4 << 15);
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pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
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pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
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val = gen_cntl >> 15;
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val &= 0x7;
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if (val == 0x4)
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printk(KERN_DEBUG "Force enabled HPET at resume\n");
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else
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BUG();
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}
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static void old_ich_force_enable_hpet(struct pci_dev *dev)
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{
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u32 val;
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u32 uninitialized_var(gen_cntl);
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if (hpet_address || force_hpet_address)
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return;
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pci_read_config_dword(dev, 0xD0, &gen_cntl);
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/*
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* Bit 17 is HPET enable bit.
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* Bit 16:15 control the HPET base address.
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*/
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val = gen_cntl >> 15;
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val &= 0x7;
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if (val & 0x4) {
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val &= 0x3;
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force_hpet_address = 0xFED00000 | (val << 12);
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printk(KERN_DEBUG "HPET at base address 0x%lx\n",
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force_hpet_address);
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cached_dev = dev;
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return;
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}
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/*
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* HPET is disabled. Trying enabling at FED00000 and check
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* whether it sticks
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*/
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gen_cntl &= (~(0x7 << 15));
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gen_cntl |= (0x4 << 15);
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pci_write_config_dword(dev, 0xD0, gen_cntl);
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pci_read_config_dword(dev, 0xD0, &gen_cntl);
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val = gen_cntl >> 15;
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val &= 0x7;
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if (val & 0x4) {
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/* HPET is enabled in HPTC. Just not reported by BIOS */
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val &= 0x3;
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force_hpet_address = 0xFED00000 | (val << 12);
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printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
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force_hpet_address);
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force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
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return;
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}
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printk(KERN_DEBUG "Failed to force enable HPET\n");
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
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old_ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
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old_ich_force_enable_hpet);
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void force_hpet_resume(void)
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{
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switch (force_hpet_resume_type) {
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case ICH_FORCE_HPET_RESUME:
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return ich_force_hpet_resume();
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case OLD_ICH_FORCE_HPET_RESUME:
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return old_ich_force_hpet_resume();
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default:
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break;
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}
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}
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#endif
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#endif
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@ -67,7 +67,7 @@ extern unsigned long force_hpet_address;
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extern int is_hpet_enabled(void);
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extern int is_hpet_enabled(void);
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extern int hpet_enable(void);
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extern int hpet_enable(void);
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extern unsigned long hpet_readl(unsigned long a);
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extern unsigned long hpet_readl(unsigned long a);
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extern void ich_force_hpet_resume(void);
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extern void force_hpet_resume(void);
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#ifdef CONFIG_HPET_EMULATE_RTC
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#ifdef CONFIG_HPET_EMULATE_RTC
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@ -2242,6 +2242,7 @@
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#define PCI_DEVICE_ID_INTEL_82801EB_5 0x24d5
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#define PCI_DEVICE_ID_INTEL_82801EB_5 0x24d5
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#define PCI_DEVICE_ID_INTEL_82801EB_6 0x24d6
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#define PCI_DEVICE_ID_INTEL_82801EB_6 0x24d6
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#define PCI_DEVICE_ID_INTEL_82801EB_11 0x24db
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#define PCI_DEVICE_ID_INTEL_82801EB_11 0x24db
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#define PCI_DEVICE_ID_INTEL_82801EB_12 0x24dc
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#define PCI_DEVICE_ID_INTEL_82801EB_13 0x24dd
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#define PCI_DEVICE_ID_INTEL_82801EB_13 0x24dd
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#define PCI_DEVICE_ID_INTEL_ESB_1 0x25a1
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#define PCI_DEVICE_ID_INTEL_ESB_1 0x25a1
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#define PCI_DEVICE_ID_INTEL_ESB_2 0x25a2
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#define PCI_DEVICE_ID_INTEL_ESB_2 0x25a2
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