[ARM] Introduce new bitmask based cache type macros
Rather than trying to (inaccurately) decode the cache type from the registers each time we need to decide what type of cache we have, use a bitmask initialized early during boot. Since the setup is a one-off initialization, we can be a little more clever and take account of the CPU architecture as well. Note that we continue to achieve the compactness on optimised kernels by forcing tests to always-false or always-true as appropriate, thereby allowing the compiler to do build-time code elimination. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King
Russell King
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90f1e08478
commit
c0e9587841
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@ -1,96 +1,52 @@
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#ifndef __ASM_ARM_CACHETYPE_H
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#define __ASM_ARM_CACHETYPE_H
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#include <asm/cputype.h>
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#define CACHEID_VIVT (1 << 0)
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#define CACHEID_VIPT_NONALIASING (1 << 1)
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#define CACHEID_VIPT_ALIASING (1 << 2)
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#define CACHEID_VIPT (CACHEID_VIPT_ALIASING|CACHEID_VIPT_NONALIASING)
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#define CACHEID_ASID_TAGGED (1 << 3)
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#define __cacheid_present(val) (val != read_cpuid_id())
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#define __cacheid_type_v7(val) ((val & (7 << 29)) == (4 << 29))
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extern unsigned int cacheid;
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#define __cacheid_vivt_prev7(val) ((val & (15 << 25)) != (14 << 25))
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#define __cacheid_vipt_prev7(val) ((val & (15 << 25)) == (14 << 25))
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#define __cacheid_vipt_nonaliasing_prev7(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25))
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#define __cacheid_vipt_aliasing_prev7(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
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#define cache_is_vivt() cacheid_is(CACHEID_VIVT)
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#define cache_is_vipt() cacheid_is(CACHEID_VIPT)
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#define cache_is_vipt_nonaliasing() cacheid_is(CACHEID_VIPT_NONALIASING)
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#define cache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_ALIASING)
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#define icache_is_vivt_asid_tagged() cacheid_is(CACHEID_ASID_TAGGED)
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#define __cacheid_vivt(val) (__cacheid_type_v7(val) ? 0 : __cacheid_vivt_prev7(val))
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#define __cacheid_vipt(val) (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_prev7(val))
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#define __cacheid_vipt_nonaliasing(val) (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_nonaliasing_prev7(val))
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#define __cacheid_vipt_aliasing(val) (__cacheid_type_v7(val) ? 0 : __cacheid_vipt_aliasing_prev7(val))
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#define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
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#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
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/*
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* VIVT caches only
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* __LINUX_ARM_ARCH__ is the minimum supported CPU architecture
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* Mask out support which will never be present on newer CPUs.
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* - v6+ is never VIVT
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* - v7+ VIPT never aliases
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*/
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#define cache_is_vivt() 1
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#define cache_is_vipt() 0
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#define cache_is_vipt_nonaliasing() 0
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#define cache_is_vipt_aliasing() 0
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#define icache_is_vivt_asid_tagged() 0
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#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
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/*
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* VIPT caches only
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*/
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#define cache_is_vivt() 0
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#define cache_is_vipt() 1
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#define cache_is_vipt_nonaliasing() \
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({ \
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unsigned int __val = read_cpuid_cachetype(); \
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__cacheid_vipt_nonaliasing(__val); \
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})
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#define cache_is_vipt_aliasing() \
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({ \
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unsigned int __val = read_cpuid_cachetype(); \
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__cacheid_vipt_aliasing(__val); \
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})
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#define icache_is_vivt_asid_tagged() \
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({ \
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unsigned int __val = read_cpuid_cachetype(); \
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__cacheid_vivt_asid_tagged_instr(__val); \
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})
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#if __LINUX_ARM_ARCH__ >= 7
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#define __CACHEID_ARCH_MIN (CACHEID_VIPT_NONALIASING | CACHEID_ASID_TAGGED)
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#elif __LINUX_ARM_ARCH__ >= 6
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#define __CACHEID_ARCH_MIN (~CACHEID_VIVT)
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#else
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#define __CACHEID_ARCH_MIN (~0)
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#endif
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/*
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* VIVT or VIPT caches. Note that this is unreliable since ARM926
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* and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.
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* There's no way to tell from the CacheType register what type (!)
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* the cache is.
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* Mask out support which isn't configured
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*/
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#define cache_is_vivt() \
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({ \
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unsigned int __val = read_cpuid_cachetype(); \
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(!__cacheid_present(__val)) || __cacheid_vivt(__val); \
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})
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#define cache_is_vipt() \
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({ \
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unsigned int __val = read_cpuid_cachetype(); \
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__cacheid_present(__val) && __cacheid_vipt(__val); \
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})
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#define cache_is_vipt_nonaliasing() \
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({ \
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unsigned int __val = read_cpuid_cachetype(); \
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__cacheid_present(__val) && \
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__cacheid_vipt_nonaliasing(__val); \
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})
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#define cache_is_vipt_aliasing() \
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({ \
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unsigned int __val = read_cpuid_cachetype(); \
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__cacheid_present(__val) && \
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__cacheid_vipt_aliasing(__val); \
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})
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#define icache_is_vivt_asid_tagged() \
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({ \
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unsigned int __val = read_cpuid_cachetype(); \
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__cacheid_present(__val) && \
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__cacheid_vivt_asid_tagged_instr(__val); \
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})
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#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
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#define __CACHEID_ALWAYS (CACHEID_VIVT)
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#define __CACHEID_NEVER (~CACHEID_VIVT)
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#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
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#define __CACHEID_ALWAYS (0)
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#define __CACHEID_NEVER (CACHEID_VIVT)
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#else
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#define __CACHEID_ALWAYS (0)
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#define __CACHEID_NEVER (0)
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#endif
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static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask)
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{
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return (__CACHEID_ALWAYS & mask) |
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(~__CACHEID_NEVER & __CACHEID_ARCH_MIN & mask & cacheid);
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}
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#endif
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@ -67,6 +67,8 @@ unsigned int processor_id;
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EXPORT_SYMBOL(processor_id);
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unsigned int __machine_arch_type;
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EXPORT_SYMBOL(__machine_arch_type);
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unsigned int cacheid;
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EXPORT_SYMBOL(cacheid);
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unsigned int __atags_pointer __initdata;
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@ -229,6 +231,25 @@ int cpu_architecture(void)
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return cpu_arch;
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}
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static void __init cacheid_init(void)
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{
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unsigned int cachetype = read_cpuid_cachetype();
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unsigned int arch = cpu_architecture();
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if (arch >= CPU_ARCH_ARMv7) {
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cacheid = CACHEID_VIPT_NONALIASING;
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if ((cachetype & (3 << 14)) == 1 << 14)
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cacheid |= CACHEID_ASID_TAGGED;
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} else if (arch >= CPU_ARCH_ARMv6) {
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if (cachetype & (1 << 23))
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cacheid = CACHEID_VIPT_ALIASING;
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else
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cacheid = CACHEID_VIPT_NONALIASING;
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} else {
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cacheid = CACHEID_VIVT;
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}
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}
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/*
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* These functions re-use the assembly code in head.S, which
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* already provide the required functionality.
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@ -278,6 +299,7 @@ static void __init setup_processor(void)
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elf_hwcap &= ~HWCAP_THUMB;
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#endif
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cacheid_init();
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cpu_proc_init();
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}
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