bnx2x: New link code
New Link code: Moving all the link related code (including the calculations, the initialization of the MAC and PHY and the external PHY's code) into a separated file. The changes from the code that used to be part of bnx2x.c (now called bnx2x_main.c) are: - Using separate structures for link inputs and link outputs to clearly identify what was configured and what is the outcome - Adding code to read external PHY FW version and print it as part of ethtool -i - Adding code to upgrade external PHY FW from ethtool -E with special magic number - Changing the link down indication to ERR level - Adding a lock on all PHY access to prevent an interrupt and setting changes to overlap - Adding support for emulation and FPGA (small chunk of code that really helps in the lab) - Adding support for 1G on BCM8706 PHY - Adding clear debug print incase of fan failure (the PHY type is now "failure") Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yaniv Rosner
David S. Miller
parent
ea4e040abc
commit
c18487ee24
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@ -66,7 +66,7 @@ obj-$(CONFIG_FEALNX) += fealnx.o
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obj-$(CONFIG_TIGON3) += tg3.o
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obj-$(CONFIG_BNX2) += bnx2.o
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obj-$(CONFIG_BNX2X) += bnx2x.o
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bnx2x-objs := bnx2x_main.o
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bnx2x-objs := bnx2x_main.o bnx2x_link.o
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spidernet-y += spider_net.o spider_net_ethtool.o
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obj-$(CONFIG_SPIDER_NET) += spidernet.o sungem_phy.o
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obj-$(CONFIG_GELIC_NET) += ps3_gelic.o
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@ -90,6 +90,12 @@
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#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
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#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
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#define REG_RD_DMAE(bp, offset, valp, len32) \
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do { \
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bnx2x_read_dmae(bp, offset, len32);\
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memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
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} while (0)
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#define REG_WR_DMAE(bp, offset, val, len32) \
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do { \
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memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \
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@ -542,11 +548,8 @@ struct bnx2x {
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int pm_cap;
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int pcie_cap;
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/* Used to synchronize phy accesses */
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spinlock_t phy_lock;
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struct work_struct reset_task;
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struct work_struct sp_task;
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struct work_struct sp_task;
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struct work_struct reset_task;
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struct timer_list timer;
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int timer_interval;
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@ -568,6 +571,8 @@ struct bnx2x {
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#define CHIP_REV_FPGA 0x0000f000
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#define CHIP_REV_IS_SLOW(bp) ((CHIP_REV(bp) == CHIP_REV_EMUL) || \
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(CHIP_REV(bp) == CHIP_REV_FPGA))
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#define CHIP_REV_IS_EMUL(bp) (CHIP_REV(bp) == CHIP_REV_EMUL)
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#define CHIP_REV_IS_FPGA(bp) (CHIP_REV(bp) == CHIP_REV_FPGA)
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#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
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#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0x0000000f)
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@ -578,84 +583,29 @@ struct bnx2x {
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u32 hw_config;
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u32 board;
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u32 serdes_config;
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u32 lane_config;
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u32 ext_phy_config;
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#define XGXS_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
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#define SERDES_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \
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PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
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u32 speed_cap_mask;
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u32 link_config;
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#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
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#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
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#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
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#define SWITCH_CFG_ONE_TIME_DETECT \
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PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT
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struct link_params link_params;
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u8 ser_lane;
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u8 rx_lane_swap;
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u8 tx_lane_swap;
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struct link_vars link_vars;
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u8 link_up;
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u8 phy_link_up;
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u32 link_config;
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u32 supported;
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/* link settings - missing defines */
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#define SUPPORTED_2500baseT_Full (1 << 15)
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u32 phy_flags;
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/*#define PHY_SERDES_FLAG 0x1*/
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#define PHY_BMAC_FLAG 0x2
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#define PHY_EMAC_FLAG 0x4
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#define PHY_XGXS_FLAG 0x8
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#define PHY_SGMII_FLAG 0x10
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#define PHY_INT_MODE_MASK_FLAG 0x300
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#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
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#define PHY_INT_MODE_LINK_READY_FLAG 0x200
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u32 phy_addr;
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/* used to synchronize phy accesses */
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struct mutex phy_mutex;
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u32 phy_id;
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u32 autoneg;
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#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
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#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
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#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
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#define AUTONEG_PARALLEL \
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SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
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#define AUTONEG_SGMII_FIBER_AUTODET \
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SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
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#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
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u32 req_autoneg;
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#define AUTONEG_SPEED 0x1
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#define AUTONEG_FLOW_CTRL 0x2
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u32 req_line_speed;
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/* link settings - missing defines */
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#define SPEED_12000 12000
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#define SPEED_12500 12500
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#define SPEED_13000 13000
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#define SPEED_15000 15000
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#define SPEED_16000 16000
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u32 req_duplex;
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u32 req_flow_ctrl;
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#define FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
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#define FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
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#define FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
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#define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
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#define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
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u32 advertising;
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/* link settings - missing defines */
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#define ADVERTISED_2500baseT_Full (1 << 15)
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u32 link_status;
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u32 line_speed;
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u32 duplex;
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u32 flow_ctrl;
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u32 bc_ver;
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@ -765,6 +715,11 @@ struct bnx2x {
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#define DMAE_LEN32_MAX 0x400
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void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
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void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
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u32 len32);
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int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
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/* MC hsi */
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#define RX_COPY_THRESH 92
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@ -890,91 +845,6 @@ struct bnx2x {
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(1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
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#define MDIO_AN_CL73_OR_37_COMPLETE \
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(MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
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MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
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#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
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MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
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#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
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MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
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#define GP_STATUS_SPEED_MASK \
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MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
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#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
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#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
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#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
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#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
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#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
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#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
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#define GP_STATUS_10G_HIG \
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MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
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#define GP_STATUS_10G_CX4 \
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MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
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#define GP_STATUS_12G_HIG \
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MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
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#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
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#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
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#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
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#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
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#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
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#define GP_STATUS_10G_KX4 \
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MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
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#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
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#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
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#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
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#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
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#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
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#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
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#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
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#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
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#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
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#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
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#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
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#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
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#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
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#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
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#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
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#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
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#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
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#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
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#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
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#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
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#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
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#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
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#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
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#define NIG_STATUS_XGXS0_LINK10G \
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NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
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#define NIG_STATUS_XGXS0_LINK_STATUS \
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NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
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#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
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NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
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#define NIG_STATUS_SERDES0_LINK_STATUS \
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NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
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#define NIG_MASK_MI_INT \
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NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
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#define NIG_MASK_XGXS0_LINK10G \
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NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
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#define NIG_MASK_XGXS0_LINK_STATUS \
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NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
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#define NIG_MASK_SERDES0_LINK_STATUS \
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NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
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#define XGXS_RESET_BITS \
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(MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
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MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
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MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
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MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
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MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
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#define SERDES_RESET_BITS \
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(MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
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MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
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MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
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MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
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#define BNX2X_MC_ASSERT_BITS \
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(GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
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GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
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@ -87,10 +87,6 @@ union init_op {
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#include "bnx2x_init_values.h"
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static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
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static void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
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u32 dst_addr, u32 len32);
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static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len);
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static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
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@ -107,9 +103,6 @@ static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
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}
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}
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#define INIT_MEM_WR(reg, data, reg_off, len) \
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bnx2x_init_str_wr(bp, reg + reg_off*4, data, len)
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static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
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u16 len)
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{
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