MIPS: Netlogic: Add MSI support for XLP
Add MSI chip and MSIX chip definitions. For MSI, we map the link interrupt to a MSI link IRQ which will do a second level of dispatch based on the MSI status register. The MSI chip definitions use the MSI enable register to enable and disable the MSI irqs. For MSI-X, we split the 32 available MSI-X vectors across the four PCIe links (8 each). These PIC interrupts generate an IRQ per link which uses a second level dispatch as well. The MSI-X chip definition uses the standard functions to enable and disable interrupts. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6270/
This commit is contained in:
Jayachandran C
Ralf Baechle
parent
27547abf36
commit
c24a8a7a99
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@ -775,6 +775,7 @@ config NLM_XLP_BOARD
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select CEVT_R4K
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select CSRC_R4K
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select IRQ_CPU
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select ARCH_SUPPORTS_MSI
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select ZONE_DMA32 if 64BIT
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select SYNC_R4K
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select SYS_HAS_EARLY_PRINTK
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@ -9,7 +9,8 @@
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#define __ASM_NETLOGIC_IRQ_H
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#include <asm/mach-netlogic/multi-node.h>
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#define NR_IRQS (64 * NLM_NR_NODES)
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#define NLM_IRQS_PER_NODE 1024
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#define NR_IRQS (NLM_IRQS_PER_NODE * NLM_NR_NODES)
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#define MIPS_CPU_IRQ_BASE 0
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@ -112,8 +112,14 @@ struct nlm_soc_info {
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struct irq_data;
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uint64_t nlm_pci_irqmask(int node);
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void nlm_setup_pic_irq(int node, int picirq, int irq, int irt);
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void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *));
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#ifdef CONFIG_PCI_MSI
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void nlm_dispatch_msi(int node, int lirq);
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void nlm_dispatch_msix(int node, int msixirq);
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#endif
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/*
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* The NR_IRQs is divided between nodes, each of them has a separate irq space
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*/
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@ -52,25 +52,42 @@
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#define PCIE_BYTE_SWAP_MEM_LIM 0x248
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#define PCIE_BYTE_SWAP_IO_BASE 0x249
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#define PCIE_BYTE_SWAP_IO_LIM 0x24A
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#define PCIE_BRIDGE_MSIX_ADDR_BASE 0x24F
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#define PCIE_BRIDGE_MSIX_ADDR_LIMIT 0x250
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#define PCIE_MSI_STATUS 0x25A
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#define PCIE_MSI_EN 0x25B
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#define PCIE_MSIX_STATUS 0x25D
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#define PCIE_INT_STATUS0 0x25F
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#define PCIE_INT_STATUS1 0x260
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#define PCIE_INT_EN0 0x261
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#define PCIE_INT_EN1 0x262
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/* PCIE_MSI_EN */
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#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF
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/* PCIE_INT_EN0 */
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#define PCIE_MSI_INT_EN (1 << 9)
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/* other */
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#define PCIE_NLINKS 4
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/* MSI addresses */
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#define MSI_ADDR_BASE 0xfffee00000ULL
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#define MSI_ADDR_SZ 0x10000
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#define MSI_LINK_ADDR(n, l) (MSI_ADDR_BASE + \
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(PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
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#define MSIX_ADDR_BASE 0xfffef00000ULL
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#define MSIX_LINK_ADDR(n, l) (MSIX_ADDR_BASE + \
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(PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
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#ifndef __ASSEMBLY__
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#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r)
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#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v)
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#define nlm_get_pcie_base(node, inst) \
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nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))
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#define nlm_get_pcie_regbase(node, inst) \
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(nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)
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int xlp_pcie_link_irt(int link);
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#ifdef CONFIG_PCI_MSI
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void xlp_init_node_msi_irqs(int node, int link);
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#else
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static inline void xlp_init_node_msi_irqs(int node, int link) {}
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#endif
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struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev);
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#endif
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#endif /* __NLM_HAL_PCIBUS_H__ */
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@ -193,14 +193,9 @@
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#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
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#define PIC_CLOCK_TIMER 7
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#define PIC_IRQ_BASE 8
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#if !defined(LOCORE) && !defined(__ASSEMBLY__)
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#define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE)
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#define PIC_IRT_LAST_IRQ 63
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#define PIC_IRQ_IS_IRT(irq) ((irq) >= PIC_IRT_FIRST_IRQ)
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/*
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* Misc
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*/
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@ -37,10 +37,9 @@
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#define PIC_UART_0_IRQ 17
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#define PIC_UART_1_IRQ 18
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#define PIC_PCIE_LINK_0_IRQ 19
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#define PIC_PCIE_LINK_1_IRQ 20
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#define PIC_PCIE_LINK_2_IRQ 21
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#define PIC_PCIE_LINK_3_IRQ 22
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#define PIC_PCIE_LINK_LEGACY_IRQ_BASE 19
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#define PIC_PCIE_LINK_LEGACY_IRQ(i) (19 + (i))
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#define PIC_EHCI_0_IRQ 23
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#define PIC_EHCI_1_IRQ 24
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@ -58,6 +57,23 @@
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#define PIC_I2C_2_IRQ 32
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#define PIC_I2C_3_IRQ 33
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#define PIC_PCIE_LINK_MSI_IRQ_BASE 44 /* 44 - 47 MSI IRQ */
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#define PIC_PCIE_LINK_MSI_IRQ(i) (44 + (i))
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/* MSI-X with second link-level dispatch */
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#define PIC_PCIE_MSIX_IRQ_BASE 48 /* 48 - 51 MSI-X IRQ */
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#define PIC_PCIE_MSIX_IRQ(i) (48 + (i))
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#define NLM_MSIX_VEC_BASE 96 /* 96 - 127 - MSIX mapped */
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#define NLM_MSI_VEC_BASE 128 /* 128 -255 - MSI mapped */
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#define NLM_PIC_INDIRECT_VEC_BASE 512
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#define NLM_GPIO_VEC_BASE 768
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#define PIC_IRQ_BASE 8
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#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
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#define PIC_IRT_LAST_IRQ 63
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#ifndef __ASSEMBLY__
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/* SMP support functions */
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@ -180,6 +180,7 @@ static void __init nlm_init_percpu_irqs(void)
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#endif
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}
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void nlm_setup_pic_irq(int node, int picirq, int irq, int irt)
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{
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struct nlm_pic_irq *pic_data;
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@ -207,24 +208,24 @@ void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *))
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static void nlm_init_node_irqs(int node)
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{
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int i, irt;
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uint64_t irqmask;
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struct nlm_soc_info *nodep;
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int i, irt;
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pr_info("Init IRQ for node %d\n", node);
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nodep = nlm_get_node(node);
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irqmask = PERCPU_IRQ_MASK;
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nodep->irqmask = PERCPU_IRQ_MASK;
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for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) {
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irt = nlm_irq_to_irt(i);
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if (irt == -1)
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if (irt == -1) /* unused irq */
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continue;
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nlm_setup_pic_irq(node, i, i, irt);
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/* set interrupts to first cpu in node */
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nodep->irqmask |= 1ull << i;
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if (irt == -2) /* not a direct PIC irq */
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continue;
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nlm_pic_init_irt(nodep->picbase, irt, i,
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node * NLM_CPUS_PER_NODE, 0);
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irqmask |= (1ull << i);
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nlm_setup_pic_irq(node, i, i, irt);
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}
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nodep->irqmask = irqmask;
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}
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void nlm_smp_irq_init(int hwcpuid)
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@ -256,6 +257,18 @@ asmlinkage void plat_irq_dispatch(void)
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return;
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}
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#if defined(CONFIG_PCI_MSI) && defined(CONFIG_CPU_XLP)
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/* PCI interrupts need a second level dispatch for MSI bits */
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if (i >= PIC_PCIE_LINK_MSI_IRQ(0) && i <= PIC_PCIE_LINK_MSI_IRQ(3)) {
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nlm_dispatch_msi(node, i);
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return;
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}
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if (i >= PIC_PCIE_MSIX_IRQ(0) && i <= PIC_PCIE_MSIX_IRQ(3)) {
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nlm_dispatch_msix(node, i);
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return;
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}
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#endif
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/* top level irq handling */
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do_IRQ(nlm_irq_to_xirq(node, i));
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}
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@ -135,9 +135,17 @@ int nlm_irq_to_irt(int irq)
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case PIC_I2C_3_IRQ:
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irt = irt + 3; break;
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}
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} else if (irq >= PIC_PCIE_LINK_0_IRQ && irq <= PIC_PCIE_LINK_3_IRQ) {
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} else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
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irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
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/* HW bug, PCI IRT entries are bad on early silicon, fix */
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irt = PIC_IRT_PCIE_LINK_INDEX(irq - PIC_PCIE_LINK_0_IRQ);
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irt = PIC_IRT_PCIE_LINK_INDEX(irq -
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PIC_PCIE_LINK_LEGACY_IRQ_BASE);
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} else if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) &&
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irq <= PIC_PCIE_LINK_MSI_IRQ(3)) {
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irt = -2;
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} else if (irq >= PIC_PCIE_MSIX_IRQ(0) &&
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irq <= PIC_PCIE_MSIX_IRQ(3)) {
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irt = -2;
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} else {
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irt = -1;
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}
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@ -60,4 +60,5 @@ obj-$(CONFIG_CPU_XLP) += pci-xlp.o
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ifdef CONFIG_PCI_MSI
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obj-$(CONFIG_CAVIUM_OCTEON_SOC) += msi-octeon.o
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obj-$(CONFIG_CPU_XLP) += msi-xlp.o
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endif
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@ -0,0 +1,494 @@
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/*
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the Broadcom
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/msi.h>
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#include <linux/mm.h>
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#include <linux/irq.h>
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#include <linux/irqdesc.h>
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#include <linux/console.h>
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#include <asm/io.h>
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#include <asm/netlogic/interrupt.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/mips-extns.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/pic.h>
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#include <asm/netlogic/xlp-hal/pcibus.h>
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#include <asm/netlogic/xlp-hal/bridge.h>
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#define XLP_MSIVEC_PER_LINK 32
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#define XLP_MSIXVEC_TOTAL 32
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#define XLP_MSIXVEC_PER_LINK 8
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/* 128 MSI irqs per node, mapped starting at NLM_MSI_VEC_BASE */
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static inline int nlm_link_msiirq(int link, int msivec)
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{
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return NLM_MSI_VEC_BASE + link * XLP_MSIVEC_PER_LINK + msivec;
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}
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static inline int nlm_irq_msivec(int irq)
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{
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return irq % XLP_MSIVEC_PER_LINK;
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}
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static inline int nlm_irq_msilink(int irq)
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{
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return (irq % (XLP_MSIVEC_PER_LINK * PCIE_NLINKS)) /
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XLP_MSIVEC_PER_LINK;
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}
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/*
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* Only 32 MSI-X vectors are possible because there are only 32 PIC
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* interrupts for MSI. We split them statically and use 8 MSI-X vectors
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* per link - this keeps the allocation and lookup simple.
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*/
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static inline int nlm_link_msixirq(int link, int bit)
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{
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return NLM_MSIX_VEC_BASE + link * XLP_MSIXVEC_PER_LINK + bit;
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}
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static inline int nlm_irq_msixvec(int irq)
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{
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return irq % XLP_MSIXVEC_TOTAL; /* works when given xirq */
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}
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static inline int nlm_irq_msixlink(int irq)
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{
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return nlm_irq_msixvec(irq) / XLP_MSIXVEC_PER_LINK;
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}
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/*
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* Per link MSI and MSI-X information, set as IRQ handler data for
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* MSI and MSI-X interrupts.
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*/
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struct xlp_msi_data {
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struct nlm_soc_info *node;
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uint64_t lnkbase;
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uint32_t msi_enabled_mask;
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uint32_t msi_alloc_mask;
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uint32_t msix_alloc_mask;
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spinlock_t msi_lock;
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};
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/*
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* MSI Chip definitions
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*
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* On XLP, there is a PIC interrupt associated with each PCIe link on the
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* chip (which appears as a PCI bridge to us). This gives us 32 MSI irqa
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* per link and 128 overall.
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*
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* When a device connected to the link raises a MSI interrupt, we get a
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* link interrupt and we then have to look at PCIE_MSI_STATUS register at
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* the bridge to map it to the IRQ
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*/
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static void xlp_msi_enable(struct irq_data *d)
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{
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struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
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unsigned long flags;
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int vec;
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vec = nlm_irq_msivec(d->irq);
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spin_lock_irqsave(&md->msi_lock, flags);
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md->msi_enabled_mask |= 1u << vec;
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nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);
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spin_unlock_irqrestore(&md->msi_lock, flags);
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}
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static void xlp_msi_disable(struct irq_data *d)
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{
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struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
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unsigned long flags;
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int vec;
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vec = nlm_irq_msivec(d->irq);
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spin_lock_irqsave(&md->msi_lock, flags);
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md->msi_enabled_mask &= ~(1u << vec);
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nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);
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spin_unlock_irqrestore(&md->msi_lock, flags);
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}
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static void xlp_msi_mask_ack(struct irq_data *d)
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{
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struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
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int link, vec;
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link = nlm_irq_msilink(d->irq);
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vec = nlm_irq_msivec(d->irq);
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xlp_msi_disable(d);
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/* Ack MSI on bridge */
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nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec);
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/* Ack at eirr and PIC */
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ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link));
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nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));
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}
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static struct irq_chip xlp_msi_chip = {
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.name = "XLP-MSI",
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.irq_enable = xlp_msi_enable,
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.irq_disable = xlp_msi_disable,
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.irq_mask_ack = xlp_msi_mask_ack,
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.irq_unmask = xlp_msi_enable,
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};
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/*
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* The MSI-X interrupt handling is different from MSI, there are 32
|
||||
* MSI-X interrupts generated by the PIC and each of these correspond
|
||||
* to a MSI-X vector (0-31) that can be assigned.
|
||||
*
|
||||
* We divide the MSI-X vectors to 8 per link and do a per-link
|
||||
* allocation
|
||||
*
|
||||
* Enable and disable done using standard MSI functions.
|
||||
*/
|
||||
static void xlp_msix_mask_ack(struct irq_data *d)
|
||||
{
|
||||
struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
|
||||
int link, msixvec;
|
||||
|
||||
msixvec = nlm_irq_msixvec(d->irq);
|
||||
link = nlm_irq_msixlink(d->irq);
|
||||
mask_msi_irq(d);
|
||||
|
||||
/* Ack MSI on bridge */
|
||||
nlm_write_reg(md->lnkbase, PCIE_MSIX_STATUS, 1u << msixvec);
|
||||
|
||||
/* Ack at eirr and PIC */
|
||||
ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));
|
||||
nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_MSIX_INDEX(msixvec));
|
||||
}
|
||||
|
||||
static struct irq_chip xlp_msix_chip = {
|
||||
.name = "XLP-MSIX",
|
||||
.irq_enable = unmask_msi_irq,
|
||||
.irq_disable = mask_msi_irq,
|
||||
.irq_mask_ack = xlp_msix_mask_ack,
|
||||
.irq_unmask = unmask_msi_irq,
|
||||
};
|
||||
|
||||
void destroy_irq(unsigned int irq)
|
||||
{
|
||||
/* nothing to do yet */
|
||||
}
|
||||
|
||||
void arch_teardown_msi_irq(unsigned int irq)
|
||||
{
|
||||
destroy_irq(irq);
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup a PCIe link for MSI. By default, the links are in
|
||||
* legacy interrupt mode. We will switch them to MSI mode
|
||||
* at the first MSI request.
|
||||
*/
|
||||
static void xlp_config_link_msi(uint64_t lnkbase, int lirq, uint64_t msiaddr)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = nlm_read_reg(lnkbase, PCIE_INT_EN0);
|
||||
if ((val & 0x200) == 0) {
|
||||
val |= 0x200; /* MSI Interrupt enable */
|
||||
nlm_write_reg(lnkbase, PCIE_INT_EN0, val);
|
||||
}
|
||||
|
||||
val = nlm_read_reg(lnkbase, 0x1); /* CMD */
|
||||
if ((val & 0x0400) == 0) {
|
||||
val |= 0x0400;
|
||||
nlm_write_reg(lnkbase, 0x1, val);
|
||||
}
|
||||
|
||||
/* Update IRQ in the PCI irq reg */
|
||||
val = nlm_read_pci_reg(lnkbase, 0xf);
|
||||
val &= ~0x1fu;
|
||||
val |= (1 << 8) | lirq;
|
||||
nlm_write_pci_reg(lnkbase, 0xf, val);
|
||||
|
||||
/* MSI addr */
|
||||
nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRH, msiaddr >> 32);
|
||||
nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRL, msiaddr & 0xffffffff);
|
||||
|
||||
/* MSI cap for bridge */
|
||||
val = nlm_read_reg(lnkbase, PCIE_BRIDGE_MSI_CAP);
|
||||
if ((val & (1 << 16)) == 0) {
|
||||
val |= 0xb << 16; /* mmc32, msi enable */
|
||||
nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_CAP, val);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Allocate a MSI vector on a link
|
||||
*/
|
||||
static int xlp_setup_msi(uint64_t lnkbase, int node, int link,
|
||||
struct msi_desc *desc)
|
||||
{
|
||||
struct xlp_msi_data *md;
|
||||
struct msi_msg msg;
|
||||
unsigned long flags;
|
||||
int msivec, irt, lirq, xirq, ret;
|
||||
uint64_t msiaddr;
|
||||
|
||||
/* Get MSI data for the link */
|
||||
lirq = PIC_PCIE_LINK_MSI_IRQ(link);
|
||||
xirq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
|
||||
md = irq_get_handler_data(xirq);
|
||||
msiaddr = MSI_LINK_ADDR(node, link);
|
||||
|
||||
spin_lock_irqsave(&md->msi_lock, flags);
|
||||
if (md->msi_alloc_mask == 0) {
|
||||
/* switch the link IRQ to MSI range */
|
||||
xlp_config_link_msi(lnkbase, lirq, msiaddr);
|
||||
irt = PIC_IRT_PCIE_LINK_INDEX(link);
|
||||
nlm_setup_pic_irq(node, lirq, lirq, irt);
|
||||
nlm_pic_init_irt(nlm_get_node(node)->picbase, irt, lirq,
|
||||
node * NLM_CPUS_PER_NODE, 1 /*en */);
|
||||
}
|
||||
|
||||
/* allocate a MSI vec, and tell the bridge about it */
|
||||
msivec = fls(md->msi_alloc_mask);
|
||||
if (msivec == XLP_MSIVEC_PER_LINK) {
|
||||
spin_unlock_irqrestore(&md->msi_lock, flags);
|
||||
return -ENOMEM;
|
||||
}
|
||||
md->msi_alloc_mask |= (1u << msivec);
|
||||
spin_unlock_irqrestore(&md->msi_lock, flags);
|
||||
|
||||
msg.address_hi = msiaddr >> 32;
|
||||
msg.address_lo = msiaddr & 0xffffffff;
|
||||
msg.data = 0xc00 | msivec;
|
||||
|
||||
xirq = xirq + msivec; /* msi mapped to global irq space */
|
||||
ret = irq_set_msi_desc(xirq, desc);
|
||||
if (ret < 0) {
|
||||
destroy_irq(xirq);
|
||||
return ret;
|
||||
}
|
||||
|
||||
write_msi_msg(xirq, &msg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Switch a link to MSI-X mode
|
||||
*/
|
||||
static void xlp_config_link_msix(uint64_t lnkbase, int lirq, uint64_t msixaddr)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = nlm_read_reg(lnkbase, 0x2C);
|
||||
if ((val & 0x80000000U) == 0) {
|
||||
val |= 0x80000000U;
|
||||
nlm_write_reg(lnkbase, 0x2C, val);
|
||||
}
|
||||
val = nlm_read_reg(lnkbase, PCIE_INT_EN0);
|
||||
if ((val & 0x200) == 0) {
|
||||
val |= 0x200; /* MSI Interrupt enable */
|
||||
nlm_write_reg(lnkbase, PCIE_INT_EN0, val);
|
||||
}
|
||||
|
||||
val = nlm_read_reg(lnkbase, 0x1); /* CMD */
|
||||
if ((val & 0x0400) == 0) {
|
||||
val |= 0x0400;
|
||||
nlm_write_reg(lnkbase, 0x1, val);
|
||||
}
|
||||
|
||||
/* Update IRQ in the PCI irq reg */
|
||||
val = nlm_read_pci_reg(lnkbase, 0xf);
|
||||
val &= ~0x1fu;
|
||||
val |= (1 << 8) | lirq;
|
||||
nlm_write_pci_reg(lnkbase, 0xf, val);
|
||||
|
||||
/* MSI-X addresses */
|
||||
nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_BASE, msixaddr >> 8);
|
||||
nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_LIMIT,
|
||||
(msixaddr + MSI_ADDR_SZ) >> 8);
|
||||
}
|
||||
|
||||
/*
|
||||
* Allocate a MSI-X vector
|
||||
*/
|
||||
static int xlp_setup_msix(uint64_t lnkbase, int node, int link,
|
||||
struct msi_desc *desc)
|
||||
{
|
||||
struct xlp_msi_data *md;
|
||||
struct msi_msg msg;
|
||||
unsigned long flags;
|
||||
int t, msixvec, lirq, xirq, ret;
|
||||
uint64_t msixaddr;
|
||||
|
||||
/* Get MSI data for the link */
|
||||
lirq = PIC_PCIE_MSIX_IRQ(link);
|
||||
xirq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0));
|
||||
md = irq_get_handler_data(xirq);
|
||||
msixaddr = MSIX_LINK_ADDR(node, link);
|
||||
|
||||
spin_lock_irqsave(&md->msi_lock, flags);
|
||||
/* switch the PCIe link to MSI-X mode at the first alloc */
|
||||
if (md->msix_alloc_mask == 0)
|
||||
xlp_config_link_msix(lnkbase, lirq, msixaddr);
|
||||
|
||||
/* allocate a MSI-X vec, and tell the bridge about it */
|
||||
t = fls(md->msix_alloc_mask);
|
||||
if (t == XLP_MSIXVEC_PER_LINK) {
|
||||
spin_unlock_irqrestore(&md->msi_lock, flags);
|
||||
return -ENOMEM;
|
||||
}
|
||||
md->msix_alloc_mask |= (1u << t);
|
||||
spin_unlock_irqrestore(&md->msi_lock, flags);
|
||||
|
||||
xirq += t;
|
||||
msixvec = nlm_irq_msixvec(xirq);
|
||||
msg.address_hi = msixaddr >> 32;
|
||||
msg.address_lo = msixaddr & 0xffffffff;
|
||||
msg.data = 0xc00 | msixvec;
|
||||
|
||||
ret = irq_set_msi_desc(xirq, desc);
|
||||
if (ret < 0) {
|
||||
destroy_irq(xirq);
|
||||
return ret;
|
||||
}
|
||||
|
||||
write_msi_msg(xirq, &msg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
|
||||
{
|
||||
struct pci_dev *lnkdev;
|
||||
uint64_t lnkbase;
|
||||
int node, link, slot;
|
||||
|
||||
lnkdev = xlp_get_pcie_link(dev);
|
||||
if (lnkdev == NULL) {
|
||||
dev_err(&dev->dev, "Could not find bridge\n");
|
||||
return 1;
|
||||
}
|
||||
slot = PCI_SLOT(lnkdev->devfn);
|
||||
link = PCI_FUNC(lnkdev->devfn);
|
||||
node = slot / 8;
|
||||
lnkbase = nlm_get_pcie_base(node, link);
|
||||
|
||||
if (desc->msi_attrib.is_msix)
|
||||
return xlp_setup_msix(lnkbase, node, link, desc);
|
||||
else
|
||||
return xlp_setup_msi(lnkbase, node, link, desc);
|
||||
}
|
||||
|
||||
void __init xlp_init_node_msi_irqs(int node, int link)
|
||||
{
|
||||
struct nlm_soc_info *nodep;
|
||||
struct xlp_msi_data *md;
|
||||
int irq, i, irt, msixvec;
|
||||
|
||||
pr_info("[%d %d] Init node PCI IRT\n", node, link);
|
||||
nodep = nlm_get_node(node);
|
||||
|
||||
/* Alloc an MSI block for the link */
|
||||
md = kzalloc(sizeof(*md), GFP_KERNEL);
|
||||
spin_lock_init(&md->msi_lock);
|
||||
md->msi_enabled_mask = 0;
|
||||
md->msi_alloc_mask = 0;
|
||||
md->msix_alloc_mask = 0;
|
||||
md->node = nodep;
|
||||
md->lnkbase = nlm_get_pcie_base(node, link);
|
||||
|
||||
/* extended space for MSI interrupts */
|
||||
irq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
|
||||
for (i = irq; i < irq + XLP_MSIVEC_PER_LINK; i++) {
|
||||
irq_set_chip_and_handler(i, &xlp_msi_chip, handle_level_irq);
|
||||
irq_set_handler_data(i, md);
|
||||
}
|
||||
|
||||
for (i = 0; i < XLP_MSIXVEC_PER_LINK; i++) {
|
||||
/* Initialize MSI-X irts to generate one interrupt per link */
|
||||
msixvec = link * XLP_MSIXVEC_PER_LINK + i;
|
||||
irt = PIC_IRT_PCIE_MSIX_INDEX(msixvec);
|
||||
nlm_pic_init_irt(nodep->picbase, irt, PIC_PCIE_MSIX_IRQ(link),
|
||||
node * NLM_CPUS_PER_NODE, 1 /* enable */);
|
||||
|
||||
/* Initialize MSI-X extended irq space for the link */
|
||||
irq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, i));
|
||||
irq_set_chip_and_handler(irq, &xlp_msix_chip, handle_level_irq);
|
||||
irq_set_handler_data(irq, md);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void nlm_dispatch_msi(int node, int lirq)
|
||||
{
|
||||
struct xlp_msi_data *md;
|
||||
int link, i, irqbase;
|
||||
u32 status;
|
||||
|
||||
link = lirq - PIC_PCIE_LINK_MSI_IRQ_BASE;
|
||||
irqbase = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
|
||||
md = irq_get_handler_data(irqbase);
|
||||
status = nlm_read_reg(md->lnkbase, PCIE_MSI_STATUS) &
|
||||
md->msi_enabled_mask;
|
||||
while (status) {
|
||||
i = __ffs(status);
|
||||
do_IRQ(irqbase + i);
|
||||
status &= status - 1;
|
||||
}
|
||||
}
|
||||
|
||||
void nlm_dispatch_msix(int node, int lirq)
|
||||
{
|
||||
struct xlp_msi_data *md;
|
||||
int link, i, irqbase;
|
||||
u32 status;
|
||||
|
||||
link = lirq - PIC_PCIE_MSIX_IRQ_BASE;
|
||||
irqbase = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0));
|
||||
md = irq_get_handler_data(irqbase);
|
||||
status = nlm_read_reg(md->lnkbase, PCIE_MSIX_STATUS);
|
||||
|
||||
/* narrow it down to the MSI-x vectors for our link */
|
||||
status = (status >> (link * XLP_MSIXVEC_PER_LINK)) &
|
||||
((1 << XLP_MSIXVEC_PER_LINK) - 1);
|
||||
|
||||
while (status) {
|
||||
i = __ffs(status);
|
||||
do_IRQ(irqbase + i);
|
||||
status &= status - 1;
|
||||
}
|
||||
}
|
||||
|
|
@ -47,6 +47,7 @@
|
|||
#include <asm/netlogic/interrupt.h>
|
||||
#include <asm/netlogic/haldefs.h>
|
||||
#include <asm/netlogic/common.h>
|
||||
#include <asm/netlogic/mips-extns.h>
|
||||
|
||||
#include <asm/netlogic/xlp-hal/iomap.h>
|
||||
#include <asm/netlogic/xlp-hal/pic.h>
|
||||
|
|
@ -162,7 +163,7 @@ struct pci_controller nlm_pci_controller = {
|
|||
.io_offset = 0x00000000UL,
|
||||
};
|
||||
|
||||
static struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev)
|
||||
struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev)
|
||||
{
|
||||
struct pci_bus *bus, *p;
|
||||
|
||||
|
|
@ -174,11 +175,6 @@ static struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev)
|
|||
return p ? bus->self : NULL;
|
||||
}
|
||||
|
||||
static inline int nlm_pci_link_to_irq(int link)
|
||||
{
|
||||
return PIC_PCIE_LINK_0_IRQ + link;
|
||||
}
|
||||
|
||||
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
struct pci_dev *lnkdev;
|
||||
|
|
@ -193,7 +189,7 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
|||
return 0;
|
||||
lnkfunc = PCI_FUNC(lnkdev->devfn);
|
||||
lnkslot = PCI_SLOT(lnkdev->devfn);
|
||||
return nlm_irq_to_xirq(lnkslot / 8, nlm_pci_link_to_irq(lnkfunc));
|
||||
return nlm_irq_to_xirq(lnkslot / 8, PIC_PCIE_LINK_LEGACY_IRQ(lnkfunc));
|
||||
}
|
||||
|
||||
/* Do platform specific device initialization at pci_enable_device() time */
|
||||
|
|
@ -257,16 +253,17 @@ static int __init pcibios_init(void)
|
|||
if (!nodep->coremask)
|
||||
continue; /* node does not exist */
|
||||
|
||||
for (link = 0; link < 4; link++) {
|
||||
for (link = 0; link < PCIE_NLINKS; link++) {
|
||||
pciebase = nlm_get_pcie_base(n, link);
|
||||
if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
|
||||
continue;
|
||||
xlp_config_pci_bswap(n, link);
|
||||
xlp_init_node_msi_irqs(n, link);
|
||||
|
||||
/* put in intpin and irq - u-boot does not */
|
||||
reg = nlm_read_pci_reg(pciebase, 0xf);
|
||||
reg &= ~0x1fu;
|
||||
reg |= (1 << 8) | nlm_pci_link_to_irq(link);
|
||||
reg |= (1 << 8) | PIC_PCIE_LINK_LEGACY_IRQ(link);
|
||||
nlm_write_pci_reg(pciebase, 0xf, reg);
|
||||
pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue