PCI: imx6: Simplify pcie_phy_poll_ack()
Simplify pcie_phy_poll_ack() by incorporating shifting into constant definition and convert the code to use 'bool'. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
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@ -112,7 +112,7 @@ struct imx6_pcie {
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#define PCIE_PHY_CTRL_RD BIT(19)
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#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
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#define PCIE_PHY_STAT_ACK_LOC 16
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#define PCIE_PHY_STAT_ACK BIT(16)
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#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
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@ -151,16 +151,16 @@ struct imx6_pcie {
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#define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5)
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#define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3)
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static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
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static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
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{
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struct dw_pcie *pci = imx6_pcie->pci;
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u32 val;
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bool val;
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u32 max_iterations = 10;
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u32 wait_counter = 0;
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do {
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val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
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val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
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val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) &
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PCIE_PHY_STAT_ACK;
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wait_counter++;
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if (val == exp_val)
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@ -184,14 +184,14 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
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val |= PCIE_PHY_CTRL_CAP_ADR;
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
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ret = pcie_phy_poll_ack(imx6_pcie, 1);
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ret = pcie_phy_poll_ack(imx6_pcie, true);
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if (ret)
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return ret;
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val = PCIE_PHY_CTRL_DATA(addr);
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
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return pcie_phy_poll_ack(imx6_pcie, 0);
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return pcie_phy_poll_ack(imx6_pcie, false);
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}
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/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
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@ -209,7 +209,7 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
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phy_ctl = PCIE_PHY_CTRL_RD;
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
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ret = pcie_phy_poll_ack(imx6_pcie, 1);
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ret = pcie_phy_poll_ack(imx6_pcie, true);
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if (ret)
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return ret;
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@ -219,7 +219,7 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
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/* deassert Read signal */
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
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return pcie_phy_poll_ack(imx6_pcie, 0);
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return pcie_phy_poll_ack(imx6_pcie, false);
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}
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static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
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@ -241,7 +241,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
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var |= PCIE_PHY_CTRL_CAP_DAT;
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
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ret = pcie_phy_poll_ack(imx6_pcie, 1);
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ret = pcie_phy_poll_ack(imx6_pcie, true);
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if (ret)
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return ret;
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@ -250,7 +250,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
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/* wait for ack de-assertion */
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ret = pcie_phy_poll_ack(imx6_pcie, 0);
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ret = pcie_phy_poll_ack(imx6_pcie, false);
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if (ret)
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return ret;
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@ -259,7 +259,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
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/* wait for ack */
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ret = pcie_phy_poll_ack(imx6_pcie, 1);
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ret = pcie_phy_poll_ack(imx6_pcie, true);
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if (ret)
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return ret;
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@ -268,7 +268,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
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/* wait for ack de-assertion */
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ret = pcie_phy_poll_ack(imx6_pcie, 0);
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ret = pcie_phy_poll_ack(imx6_pcie, false);
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if (ret)
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return ret;
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