bnx2x: Pre emphasis configuration
Supporting non-default pre-emphasis settings for the internal and some external PHYs Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
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@ -178,36 +178,21 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
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u32 rdma_mac_lower;
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u32 serdes_config;
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/* for external PHY, or forced mode or during AN */
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#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
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#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 16
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#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF
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#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
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#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0x0000ffff
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#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 0
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#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000
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#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
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u16 serdes_tx_driver_pre_emphasis[16];
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u16 serdes_rx_driver_equalizer[16];
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u32 xgxs_config_lane0;
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u32 xgxs_config_lane1;
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u32 xgxs_config_lane2;
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u32 xgxs_config_lane3;
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/* for external PHY, or forced mode or during AN */
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#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
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#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT 16
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u32 Reserved0[16]; /* 0x158 */
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#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK 0x0000ffff
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#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT 0
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/* for external PHY, or forced mode or during AN */
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u16 xgxs_config_rx[4]; /* 0x198 */
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u16 xgxs_tx_driver_pre_emphasis_lane0[16];
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u16 xgxs_tx_driver_pre_emphasis_lane1[16];
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u16 xgxs_tx_driver_pre_emphasis_lane2[16];
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u16 xgxs_tx_driver_pre_emphasis_lane3[16];
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u16 xgxs_config_tx[4]; /* 0x1A0 */
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u16 xgxs_rx_driver_equalizer_lane0[16];
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u16 xgxs_rx_driver_equalizer_lane1[16];
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u16 xgxs_rx_driver_equalizer_lane2[16];
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u16 xgxs_rx_driver_equalizer_lane3[16];
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u32 Reserved1[64]; /* 0x1A8 */
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u32 lane_config;
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#define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
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@ -1758,33 +1758,39 @@ static void bnx2x_set_gmii_tx_driver(struct link_params *params)
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struct bnx2x *bp = params->bp;
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u16 lp_up2;
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u16 tx_driver;
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u16 bank;
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/* read precomp */
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_OVER_1G,
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MDIO_OVER_1G_LP_UP2, &lp_up2);
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_TX0,
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MDIO_TX0_TX_DRIVER, &tx_driver);
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/* bits [10:7] at lp_up2, positioned at [15:12] */
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lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
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MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
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MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
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if ((lp_up2 != 0) &&
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(lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK))) {
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/* replace tx_driver bits [15:12] */
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tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
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tx_driver |= lp_up2;
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CL45_WR_OVER_CL22(bp, params->port,
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if (lp_up2 == 0)
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return;
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for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
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bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_TX0,
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MDIO_TX0_TX_DRIVER, tx_driver);
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bank,
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MDIO_TX0_TX_DRIVER, &tx_driver);
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/* replace tx_driver bits [15:12] */
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if (lp_up2 !=
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(tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
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tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
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tx_driver |= lp_up2;
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CL45_WR_OVER_CL22(bp, params->port,
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params->phy_addr,
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bank,
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MDIO_TX0_TX_DRIVER, tx_driver);
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}
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}
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}
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@ -2890,31 +2896,40 @@ static void bnx2x_ext_phy_set_pause(struct link_params *params,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_ADV_PAUSE, val);
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}
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static void bnx2x_set_preemphasis(struct link_params *params)
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{
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u16 bank, i = 0;
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struct bnx2x *bp = params->bp;
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for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
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bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
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CL45_WR_OVER_CL22(bp, params->port,
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params->phy_addr,
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bank,
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MDIO_RX0_RX_EQ_BOOST,
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params->xgxs_config_rx[i]);
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}
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for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
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bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
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CL45_WR_OVER_CL22(bp, params->port,
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params->phy_addr,
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bank,
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MDIO_TX0_TX_DRIVER,
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params->xgxs_config_tx[i]);
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}
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}
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static void bnx2x_init_internal_phy(struct link_params *params,
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struct link_vars *vars)
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{
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struct bnx2x *bp = params->bp;
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u8 port = params->port;
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if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
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u16 bank, rx_eq;
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rx_eq = ((params->serdes_config &
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PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >>
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PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT);
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DP(NETIF_MSG_LINK, "setting rx eq to 0x%x\n", rx_eq);
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for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL;
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bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0)) {
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CL45_WR_OVER_CL22(bp, port,
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params->phy_addr,
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bank ,
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MDIO_RX0_RX_EQ_BOOST,
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((rx_eq &
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MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) |
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MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL));
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}
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if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
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(params->feature_config_flags &
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FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
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bnx2x_set_preemphasis(params);
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/* forced speed requested? */
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if (vars->line_speed != SPEED_AUTO_NEG) {
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@ -3038,6 +3053,35 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
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}
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DP(NETIF_MSG_LINK, "XGXS 8706 is initialized "
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"after %d ms\n", cnt);
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if ((params->feature_config_flags &
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FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
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u8 i;
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u16 reg;
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for (i = 0; i < 4; i++) {
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reg = MDIO_XS_8706_REG_BANK_RX0 +
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i*(MDIO_XS_8706_REG_BANK_RX1 -
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MDIO_XS_8706_REG_BANK_RX0);
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bnx2x_cl45_read(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_XS_DEVAD,
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reg, &val);
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/* Clear first 3 bits of the control */
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val &= ~0x7;
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/* Set control bits according to
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configuation */
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val |= (params->xgxs_config_rx[i] &
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0x7);
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DP(NETIF_MSG_LINK, "Setting RX"
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"Equalizer to BCM8706 reg 0x%x"
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" <-- val 0x%x\n", reg, val);
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bnx2x_cl45_write(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_XS_DEVAD,
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reg, val);
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}
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}
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/* Force speed */
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/* First enable LASI */
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bnx2x_cl45_write(bp, params->port,
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@ -3170,6 +3214,28 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
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ext_phy_addr, MDIO_PMA_DEVAD,
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MDIO_PMA_REG_LASI_CTRL, 1);
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}
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/* Set TX PreEmphasis if needed */
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if ((params->feature_config_flags &
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FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
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DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
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"TX_CTRL2 0x%x\n",
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params->xgxs_config_tx[0],
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params->xgxs_config_tx[1]);
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bnx2x_cl45_write(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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MDIO_PMA_REG_8726_TX_CTRL1,
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params->xgxs_config_tx[0]);
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bnx2x_cl45_write(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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MDIO_PMA_REG_8726_TX_CTRL2,
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params->xgxs_config_tx[1]);
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}
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
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@ -77,7 +77,6 @@ struct link_params {
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#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
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u16 hw_led_mode; /* part of the hw_config read from the shmem */
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u32 serdes_config;
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u32 lane_config;
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u32 ext_phy_config;
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#define XGXS_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \
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@ -89,6 +88,9 @@ struct link_params {
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/* phy_addr populated by the CLC */
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u8 phy_addr;
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u16 xgxs_config_rx[4]; /* preemphasis values for the rx side */
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u16 xgxs_config_tx[4]; /* preemphasis values for the tx side */
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u32 feature_config_flags;
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#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
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#define FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED (2<<0)
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@ -7550,6 +7550,15 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
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SHARED_HW_CFG_LED_MODE_MASK) >>
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SHARED_HW_CFG_LED_MODE_SHIFT);
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bp->link_params.feature_config_flags = 0;
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val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
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if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
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bp->link_params.feature_config_flags |=
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FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
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else
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bp->link_params.feature_config_flags &=
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~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
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val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
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bp->common.bc_ver = val;
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BNX2X_DEV_INFO("bc_ver %X\n", val);
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@ -7972,12 +7981,11 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
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int port = BP_PORT(bp);
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u32 val, val2;
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u32 config;
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u16 i;
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bp->link_params.bp = bp;
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bp->link_params.port = port;
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bp->link_params.serdes_config =
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SHMEM_RD(bp, dev_info.port_hw_config[port].serdes_config);
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bp->link_params.lane_config =
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SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
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bp->link_params.ext_phy_config =
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bp->port.link_config =
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SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
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/* Get the 4 lanes xgxs config rx and tx */
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for (i = 0; i < 2; i++) {
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val = SHMEM_RD(bp,
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dev_info.port_hw_config[port].xgxs_config_rx[i<<1]);
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bp->link_params.xgxs_config_rx[i << 1] = ((val>>16) & 0xffff);
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bp->link_params.xgxs_config_rx[(i << 1) + 1] = (val & 0xffff);
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val = SHMEM_RD(bp,
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dev_info.port_hw_config[port].xgxs_config_tx[i<<1]);
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bp->link_params.xgxs_config_tx[i << 1] = ((val>>16) & 0xffff);
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bp->link_params.xgxs_config_tx[(i << 1) + 1] = (val & 0xffff);
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}
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config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
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if (config & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_ENABLED)
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bp->link_params.feature_config_flags |=
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bp->link_params.feature_config_flags &=
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~FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED;
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BNX2X_DEV_INFO("serdes_config 0x%08x lane_config 0x%08x\n"
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KERN_INFO " ext_phy_config 0x%08x speed_cap_mask 0x%08x"
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" link_config 0x%08x\n",
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bp->link_params.serdes_config,
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BNX2X_DEV_INFO("lane_config 0x%08x ext_phy_config 0x%08x"
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" speed_cap_mask 0x%08x link_config 0x%08x\n",
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bp->link_params.lane_config,
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bp->link_params.ext_phy_config,
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bp->link_params.speed_cap_mask, bp->port.link_config);
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@ -5603,6 +5603,42 @@
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#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
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#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
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#define MDIO_REG_BANK_TX1 0x8070
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#define MDIO_TX1_TX_DRIVER 0x17
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#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
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#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
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#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
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#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
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#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
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#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
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#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
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#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
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#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
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#define MDIO_REG_BANK_TX2 0x8080
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#define MDIO_TX2_TX_DRIVER 0x17
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#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
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#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
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#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
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#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
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#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
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#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
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#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
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#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
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#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
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#define MDIO_REG_BANK_TX3 0x8090
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#define MDIO_TX3_TX_DRIVER 0x17
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#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
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#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
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#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
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#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
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#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
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#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
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#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
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#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
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#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
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#define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
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#define MDIO_BLOCK0_XGXS_CONTROL 0x10
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