[MIPS] Fix timer/performance interrupt detection
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -1372,12 +1372,12 @@ void __init per_cpu_trap_init(void)
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*/
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*/
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if (cpu_has_mips_r2) {
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if (cpu_has_mips_r2) {
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cp0_compare_irq = (read_c0_intctl () >> 29) & 7;
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cp0_compare_irq = (read_c0_intctl () >> 29) & 7;
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cp0_perfcount_irq = -1;
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cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7;
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if (cp0_perfcount_irq == cp0_compare_irq)
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cp0_perfcount_irq = -1;
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} else {
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} else {
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cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
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cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
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cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7;
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cp0_perfcount_irq = -1;
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if (cp0_perfcount_irq != cp0_compare_irq)
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cp0_perfcount_irq = -1;
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}
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}
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#ifdef CONFIG_MIPS_MT_SMTC
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#ifdef CONFIG_MIPS_MT_SMTC
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