arm64: v8.3: Support for weaker release consistency
ARMv8.3 adds new instructions to support Release Consistent processor consistent (RCpc) model, which is weaker than the RCsc model. Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -174,6 +174,8 @@ infrastructure:
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x--------------------------------------------------x
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x--------------------------------------------------x
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| Name | bits | visible |
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| Name | bits | visible |
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|--------------------------------------------------|
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|--------------------------------------------------|
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| LRCPC | [23-20] | y |
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|--------------------------------------------------|
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| FCMA | [19-16] | y |
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| FCMA | [19-16] | y |
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|--------------------------------------------------|
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|--------------------------------------------------|
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| JSCVT | [15-12] | y |
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| JSCVT | [15-12] | y |
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@ -157,6 +157,7 @@
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#define ID_AA64ISAR0_AES_SHIFT 4
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#define ID_AA64ISAR0_AES_SHIFT 4
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/* id_aa64isar1 */
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/* id_aa64isar1 */
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#define ID_AA64ISAR1_LRCPC_SHIFT 20
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#define ID_AA64ISAR1_FCMA_SHIFT 16
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#define ID_AA64ISAR1_FCMA_SHIFT 16
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#define ID_AA64ISAR1_JSCVT_SHIFT 12
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#define ID_AA64ISAR1_JSCVT_SHIFT 12
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@ -34,5 +34,6 @@
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#define HWCAP_ASIMDRDM (1 << 12)
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#define HWCAP_ASIMDRDM (1 << 12)
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#define HWCAP_JSCVT (1 << 13)
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#define HWCAP_JSCVT (1 << 13)
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#define HWCAP_FCMA (1 << 14)
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#define HWCAP_FCMA (1 << 14)
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#define HWCAP_LRCPC (1 << 15)
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#endif /* _UAPI__ASM_HWCAP_H */
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#endif /* _UAPI__ASM_HWCAP_H */
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@ -98,6 +98,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
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};
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};
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static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
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static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
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ARM64_FTR_END,
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ARM64_FTR_END,
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@ -896,6 +897,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
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HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
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HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
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HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
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HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
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HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
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HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
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HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
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{},
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{},
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};
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};
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@ -67,6 +67,7 @@ static const char *const hwcap_str[] = {
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"asimdrdm",
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"asimdrdm",
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"jscvt",
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"jscvt",
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"fcma",
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"fcma",
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"lrcpc",
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NULL
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NULL
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};
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};
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