Merge branch 'mailbox-for-next' of git://git.linaro.org/landing-teams/working/fujitsu/integration
Pull mailbox updates from Jussi Brar: "New driver and DT bindings for MHU controller integrated on Amlogic Meson platform" * 'mailbox-for-next' of git://git.linaro.org/landing-teams/working/fujitsu/integration: dt-bindings: mailbox: Add Amlogic Meson MHU Bindings mailbox: Add Platform Message-Handling-Unit variant driver
This commit is contained in:
Linus Torvalds
commit
c6594fc6af
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@ -0,0 +1,34 @@
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Amlogic Meson MHU Mailbox Driver
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================================
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The Amlogic's Meson SoCs Message-Handling-Unit (MHU) is a mailbox controller
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that has 3 independent channels/links to communicate with remote processor(s).
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MHU links are hardwired on a platform. A link raises interrupt for any
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received data. However, there is no specified way of knowing if the sent
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data has been read by the remote. This driver assumes the sender polls
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STAT register and the remote clears it after having read the data.
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Mailbox Device Node:
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====================
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Required properties:
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--------------------
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- compatible: Shall be "amlogic,meson-gxbb-mhu"
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- reg: Contains the mailbox register address range (base
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address and length)
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- #mbox-cells Shall be 1 - the index of the channel needed.
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- interrupts: Contains the interrupt information corresponding to
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each of the 2 links of MHU.
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Example:
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--------
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mailbox: mailbox@c883c404 {
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#mbox-cells = <1>;
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compatible = "amlogic,meson-gxbb-mhu";
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reg = <0 0xc883c404 0 0x4c>;
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interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
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<0 209 IRQ_TYPE_EDGE_RISING>,
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<0 210 IRQ_TYPE_EDGE_RISING>;
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#mbox-cells = <1>;
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};
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@ -15,6 +15,16 @@ config ARM_MHU
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The controller has 3 mailbox channels, the last of which can be
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used in Secure mode only.
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config PLATFORM_MHU
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tristate "Platform MHU Mailbox"
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depends on OF
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depends on HAS_IOMEM
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help
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Say Y here if you want to build a platform specific variant MHU
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controller driver.
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The controller has a maximum of 3 mailbox channels, the last of
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which can be used in Secure mode only.
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config PL320_MBOX
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bool "ARM PL320 Mailbox"
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depends on ARM_AMBA
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@ -6,6 +6,8 @@ obj-$(CONFIG_MAILBOX_TEST) += mailbox-test.o
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obj-$(CONFIG_ARM_MHU) += arm_mhu.o
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obj-$(CONFIG_PLATFORM_MHU) += platform_mhu.o
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obj-$(CONFIG_PL320_MBOX) += pl320-ipc.o
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obj-$(CONFIG_OMAP2PLUS_MBOX) += omap-mailbox.o
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@ -0,0 +1,205 @@
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/*
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* Copyright (C) 2016 BayLibre SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Synchronised with arm_mhu.c from :
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* Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
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* Copyright (C) 2015 Linaro Ltd.
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* Author: Jassi Brar <jaswinder.singh@linaro.org>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/mailbox_controller.h>
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#define INTR_SET_OFS 0x0
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#define INTR_STAT_OFS 0x4
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#define INTR_CLR_OFS 0x8
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#define MHU_SEC_OFFSET 0x0
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#define MHU_LP_OFFSET 0xc
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#define MHU_HP_OFFSET 0x18
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#define TX_REG_OFFSET 0x24
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#define MHU_CHANS 3
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struct platform_mhu_link {
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int irq;
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void __iomem *tx_reg;
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void __iomem *rx_reg;
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};
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struct platform_mhu {
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void __iomem *base;
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struct platform_mhu_link mlink[MHU_CHANS];
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struct mbox_chan chan[MHU_CHANS];
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struct mbox_controller mbox;
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};
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static irqreturn_t platform_mhu_rx_interrupt(int irq, void *p)
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{
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struct mbox_chan *chan = p;
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struct platform_mhu_link *mlink = chan->con_priv;
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u32 val;
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val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS);
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if (!val)
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return IRQ_NONE;
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mbox_chan_received_data(chan, (void *)&val);
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writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
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return IRQ_HANDLED;
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}
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static bool platform_mhu_last_tx_done(struct mbox_chan *chan)
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{
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struct platform_mhu_link *mlink = chan->con_priv;
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u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
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return (val == 0);
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}
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static int platform_mhu_send_data(struct mbox_chan *chan, void *data)
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{
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struct platform_mhu_link *mlink = chan->con_priv;
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u32 *arg = data;
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writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
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return 0;
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}
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static int platform_mhu_startup(struct mbox_chan *chan)
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{
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struct platform_mhu_link *mlink = chan->con_priv;
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u32 val;
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int ret;
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val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
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writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
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ret = request_irq(mlink->irq, platform_mhu_rx_interrupt,
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IRQF_SHARED, "platform_mhu_link", chan);
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if (ret) {
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dev_err(chan->mbox->dev,
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"Unable to acquire IRQ %d\n", mlink->irq);
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return ret;
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}
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return 0;
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}
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static void platform_mhu_shutdown(struct mbox_chan *chan)
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{
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struct platform_mhu_link *mlink = chan->con_priv;
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free_irq(mlink->irq, chan);
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}
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static const struct mbox_chan_ops platform_mhu_ops = {
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.send_data = platform_mhu_send_data,
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.startup = platform_mhu_startup,
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.shutdown = platform_mhu_shutdown,
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.last_tx_done = platform_mhu_last_tx_done,
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};
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static int platform_mhu_probe(struct platform_device *pdev)
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{
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int i, err;
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struct platform_mhu *mhu;
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struct device *dev = &pdev->dev;
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struct resource *res;
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int platform_mhu_reg[MHU_CHANS] = {
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MHU_SEC_OFFSET, MHU_LP_OFFSET, MHU_HP_OFFSET
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};
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/* Allocate memory for device */
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mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
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if (!mhu)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mhu->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(mhu->base)) {
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dev_err(dev, "ioremap failed\n");
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return PTR_ERR(mhu->base);
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}
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for (i = 0; i < MHU_CHANS; i++) {
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mhu->chan[i].con_priv = &mhu->mlink[i];
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mhu->mlink[i].irq = platform_get_irq(pdev, i);
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if (mhu->mlink[i].irq < 0) {
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dev_err(dev, "failed to get irq%d\n", i);
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return mhu->mlink[i].irq;
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}
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mhu->mlink[i].rx_reg = mhu->base + platform_mhu_reg[i];
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mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET;
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}
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mhu->mbox.dev = dev;
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mhu->mbox.chans = &mhu->chan[0];
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mhu->mbox.num_chans = MHU_CHANS;
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mhu->mbox.ops = &platform_mhu_ops;
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mhu->mbox.txdone_irq = false;
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mhu->mbox.txdone_poll = true;
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mhu->mbox.txpoll_period = 1;
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platform_set_drvdata(pdev, mhu);
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err = mbox_controller_register(&mhu->mbox);
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if (err) {
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dev_err(dev, "Failed to register mailboxes %d\n", err);
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return err;
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}
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dev_info(dev, "Platform MHU Mailbox registered\n");
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return 0;
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}
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static int platform_mhu_remove(struct platform_device *pdev)
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{
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struct platform_mhu *mhu = platform_get_drvdata(pdev);
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mbox_controller_unregister(&mhu->mbox);
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return 0;
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}
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static const struct of_device_id platform_mhu_dt_ids[] = {
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{ .compatible = "amlogic,meson-gxbb-mhu", },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, platform_mhu_dt_ids);
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static struct platform_driver platform_mhu_driver = {
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.probe = platform_mhu_probe,
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.remove = platform_mhu_remove,
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.driver = {
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.name = "platform-mhu",
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.of_match_table = platform_mhu_dt_ids,
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},
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};
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module_platform_driver(platform_mhu_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:platform-mhu");
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MODULE_DESCRIPTION("Platform MHU Driver");
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MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
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