ARM: S5PC1XX: Change clksrc_clks to use array of clocks
Remove the individual 'struct clksrc_clks' and place them into an array so that we can simply use s3c_register_clksrcs to register tham all in one go. Since the spdif clock relies on the audio clock, move the audio clocks into their own arrary. Thanks to Marek Szyprowski for testing and pointing out the four clocks what where missed from the clock list. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Ben Dooks
parent
1d026d9b16
commit
c837e88cf9
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@ -534,14 +534,44 @@ static struct clksrc_sources clkset_audio2 = {
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.nr_sources = ARRAY_SIZE(clkset_audio2_list),
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};
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static struct clksrc_clk clk_audio0;
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static struct clksrc_clk clk_audio1;
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static struct clksrc_clk clk_audio2;
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static struct clksrc_clk clksrc_audio[] = {
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{
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.clk = {
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.name = "audio-bus",
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.id = 0,
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.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0,
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clkset_audio0,
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.reg_div = { .reg = S5PC100_CLKDIV4, .shift = 12, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, },
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}, {
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.clk = {
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.name = "audio-bus",
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.id = 1,
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.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1,
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clkset_audio1,
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.reg_div = { .reg = S5PC100_CLKDIV4, .shift = 16, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, },
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}, {
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.clk = {
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.name = "audio-bus",
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.id = 2,
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.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2,
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clkset_audio2,
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.reg_div = { .reg = S5PC100_CLKDIV4, .shift = 20, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, },
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},
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};
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static struct clk *clkset_spdif_list[] = {
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&clk_audio0.clk,
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&clk_audio1.clk,
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&clk_audio2.clk,
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&clksrc_audio[0].clk,
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&clksrc_audio[1].clk,
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&clksrc_audio[2].clk,
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};
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static struct clksrc_sources clkset_spdif = {
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@ -585,195 +615,136 @@ static struct clksrc_sources clkset_usbhost = {
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.nr_sources = ARRAY_SIZE(clkset_usbhost_list),
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};
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static struct clksrc_clk clk_spi0 = {
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.clk = {
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.name = "spi_bus",
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.id = 0,
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.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0,
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.enable = s5pc100_sclk0_ctrl,
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static struct clksrc_clk clksrc_clks[] = {
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{
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.clk = {
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.name = "spi_bus",
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.id = 0,
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.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0,
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clkset_spi,
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.reg_div = { .reg = S5PC100_CLKDIV2, .shift = 4, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC1, .shift = 4, .size = 2, },
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};
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static struct clksrc_clk clk_spi1 = {
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.clk = {
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.name = "spi_bus",
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.id = 1,
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.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1,
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clkset_spi,
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.reg_div = { .reg = S5PC100_CLKDIV2, .shift = 8, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC1, .shift = 8, .size = 2, },
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};
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static struct clksrc_clk clk_spi2 = {
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.clk = {
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.name = "spi_bus",
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.id = 2,
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.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2,
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clkset_spi,
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.reg_div = { .reg = S5PC100_CLKDIV2, .shift = 12, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, },
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};
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static struct clksrc_clk clk_uart_uclk1 = {
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.clk = {
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.name = "uclk1",
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.id = -1,
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.ctrlbit = S5PC100_CLKGATE_SCLK0_UART,
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clkset_uart,
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.reg_div = { .reg = S5PC100_CLKDIV2, .shift = 0, .size = 3, },
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.reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, },
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};
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static struct clksrc_clk clk_audio0 = {
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.clk = {
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.name = "audio-bus",
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.id = 0,
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.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0,
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clkset_audio0,
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.reg_div = { .reg = S5PC100_CLKDIV4, .shift = 12, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, },
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};
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static struct clksrc_clk clk_audio1 = {
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.clk = {
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.name = "audio-bus",
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.id = 1,
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.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1,
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clkset_audio1,
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.reg_div = { .reg = S5PC100_CLKDIV4, .shift = 16, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, },
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};
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static struct clksrc_clk clk_audio2 = {
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.clk = {
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.name = "audio-bus",
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.id = 2,
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.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2,
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clkset_audio2,
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.reg_div = { .reg = S5PC100_CLKDIV4, .shift = 20, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, },
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};
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static struct clksrc_clk clk_spdif = {
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.clk = {
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.name = "spdif",
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.id = -1,
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},
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.sources = &clkset_spdif,
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.reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, },
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};
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static struct clksrc_clk clk_lcd = {
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.clk = {
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.name = "lcd",
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.id = -1,
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.ctrlbit = S5PC100_CLKGATE_SCLK1_LCD,
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clkset_lcd_fimc,
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.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 12, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 12, .size = 2, },
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};
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static struct clksrc_clk clk_fimc0 = {
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.clk = {
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.name = "fimc",
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.id = 0,
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.ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0,
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clkset_lcd_fimc,
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.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 16, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 16, .size = 2, },
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};
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static struct clksrc_clk clk_fimc1 = {
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.clk = {
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.name = "fimc",
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.id = 1,
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.ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1,
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clkset_lcd_fimc,
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.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 20, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 20, .size = 2, },
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};
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static struct clksrc_clk clk_fimc2 = {
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.clk = {
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.name = "fimc",
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.id = 2,
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.ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2,
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clkset_lcd_fimc,
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.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 24, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, },
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};
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static struct clksrc_clk clk_mmc0 = {
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.clk = {
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.name = "mmc_bus",
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.id = 0,
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.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0,
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clkset_mmc,
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.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 0, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 0, .size = 2, },
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};
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static struct clksrc_clk clk_mmc1 = {
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.clk = {
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.name = "mmc_bus",
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.id = 1,
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.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1,
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clkset_mmc,
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.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 4, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 4, .size = 2, },
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};
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static struct clksrc_clk clk_mmc2 = {
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.clk = {
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.name = "mmc_bus",
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.id = 2,
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.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2,
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clkset_mmc,
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.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 8, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, },
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};
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static struct clksrc_clk clk_usbhost = {
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.clk = {
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.name = "usbhost",
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.id = -1,
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.ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST,
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clkset_usbhost,
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.reg_div = { .reg = S5PC100_CLKDIV2, .shift = 20, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC1, .shift = 20, .size = 2, },
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},
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.sources = &clkset_spi,
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.reg_div = { .reg = S5PC100_CLKDIV2, .shift = 4, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC1, .shift = 4, .size = 2, },
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}, {
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.clk = {
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.name = "spi_bus",
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.id = 1,
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.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1,
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clkset_spi,
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.reg_div = { .reg = S5PC100_CLKDIV2, .shift = 8, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC1, .shift = 8, .size = 2, },
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}, {
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.clk = {
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.name = "spi_bus",
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.id = 2,
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.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2,
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clkset_spi,
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.reg_div = { .reg = S5PC100_CLKDIV2, .shift = 12, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, },
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}, {
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.clk = {
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.name = "uclk1",
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.id = -1,
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.ctrlbit = S5PC100_CLKGATE_SCLK0_UART,
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clkset_uart,
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.reg_div = { .reg = S5PC100_CLKDIV2, .shift = 0, .size = 3, },
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.reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, },
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}, {
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.clk = {
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.name = "spdif",
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.id = -1,
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},
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.sources = &clkset_spdif,
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.reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, },
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}, {
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.clk = {
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.name = "lcd",
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.id = -1,
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.ctrlbit = S5PC100_CLKGATE_SCLK1_LCD,
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clkset_lcd_fimc,
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.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 12, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 12, .size = 2, },
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}, {
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.clk = {
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.name = "fimc",
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.id = 0,
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.ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0,
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clkset_lcd_fimc,
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.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 16, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 16, .size = 2, },
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}, {
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.clk = {
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.name = "fimc",
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.id = 1,
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.ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1,
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clkset_lcd_fimc,
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.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 20, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 20, .size = 2, },
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}, {
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.clk = {
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.name = "fimc",
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.id = 2,
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.ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2,
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clkset_lcd_fimc,
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.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 24, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, },
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}, {
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.clk = {
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.name = "mmc_bus",
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.id = 0,
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.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0,
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clkset_mmc,
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.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 0, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 0, .size = 2, },
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}, {
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.clk = {
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.name = "mmc_bus",
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.id = 1,
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.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1,
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clkset_mmc,
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.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 4, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 4, .size = 2, },
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}, {
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.clk = {
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.name = "mmc_bus",
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.id = 2,
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.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2,
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clkset_mmc,
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.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 8, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, },
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}, {
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.clk = {
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.name = "usbhost",
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.id = -1,
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.ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST,
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clkset_usbhost,
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.reg_div = { .reg = S5PC100_CLKDIV2, .shift = 20, .size = 4, },
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.reg_src = { .reg = S5PC100_CLKSRC1, .shift = 20, .size = 2, },
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}
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};
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/* Clock initialisation code */
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@ -785,22 +756,6 @@ static struct clksrc_clk *init_parents[] = {
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&clk_mout_onenand,
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&clk_mout_epll,
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&clk_mout_hpll,
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&clk_spi0,
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&clk_spi1,
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&clk_spi2,
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&clk_uart_uclk1,
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&clk_audio0,
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&clk_audio1,
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&clk_audio2,
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&clk_spdif,
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&clk_lcd,
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&clk_fimc0,
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&clk_fimc1,
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&clk_fimc2,
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&clk_mmc0,
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&clk_mmc1,
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&clk_mmc2,
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&clk_usbhost,
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};
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||||
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
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||||
|
|
@ -867,6 +822,12 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
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|||
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||||
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
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||||
s3c_set_clksrc(init_parents[ptr], true);
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||||
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||||
for (ptr = 0; ptr < ARRAY_SIZE(clksrc_audio); ptr++)
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||||
s3c_set_clksrc(clksrc_audio + ptr, true);
|
||||
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||||
for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
|
||||
s3c_set_clksrc(clksrc_clks + ptr, true);
|
||||
}
|
||||
|
||||
static struct clk *clks[] __initdata = {
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||||
|
|
@ -875,8 +836,13 @@ static struct clk *clks[] __initdata = {
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|||
&clk_dout_d0_bus,
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||||
&clk_dout_pclkd0,
|
||||
&clk_dout_apll2,
|
||||
&clk_mout_apll.clk,
|
||||
&clk_mout_mpll.clk,
|
||||
&clk_mout_epll.clk,
|
||||
&clk_mout_hpll.clk,
|
||||
&clk_mout_am.clk,
|
||||
&clk_dout_d1_bus,
|
||||
&clk_mout_onenand.clk,
|
||||
&clk_dout_pclkd1,
|
||||
&clk_dout_mpll2,
|
||||
&clk_dout_cam,
|
||||
|
|
@ -890,30 +856,6 @@ static struct clk *clks[] __initdata = {
|
|||
&clk_arm,
|
||||
};
|
||||
|
||||
/* simplest change - will aggregate clocks later */
|
||||
static struct clksrc_clk *clks_src[] = {
|
||||
&clk_mout_apll,
|
||||
&clk_mout_mpll,
|
||||
&clk_mout_onenand,
|
||||
&clk_mout_epll,
|
||||
&clk_spi0,
|
||||
&clk_spi1,
|
||||
&clk_spi2,
|
||||
&clk_uart_uclk1,
|
||||
&clk_audio0,
|
||||
&clk_audio1,
|
||||
&clk_audio2,
|
||||
&clk_spdif,
|
||||
&clk_lcd,
|
||||
&clk_fimc0,
|
||||
&clk_fimc1,
|
||||
&clk_fimc2,
|
||||
&clk_mmc0,
|
||||
&clk_mmc1,
|
||||
&clk_mmc2,
|
||||
&clk_usbhost,
|
||||
};
|
||||
|
||||
void __init s5pc100_register_clocks(void)
|
||||
{
|
||||
struct clk *clkp;
|
||||
|
|
@ -929,6 +871,6 @@ void __init s5pc100_register_clocks(void)
|
|||
}
|
||||
}
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++)
|
||||
s3c_register_clksrc(clks_src[ptr], 1);
|
||||
s3c_register_clksrc(clksrc_audio, ARRAY_SIZE(clksrc_audio));
|
||||
s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue