Merge branch 'GEHC-Bx50-Switch-Support'
Sebastian Reichel says: ==================== GEHC Bx50 Switch Support This adds support for the internal switch found in GE Healthcare B450v3, B650v3 and B850v3. All devices use a GPIO bitbanged MDIO bus to communicate with the switch and a PCIe based network card for exchanging network data. The cpu network data link requires, that the switch's internal phy interface is enabled, so support for that is added by the first patch in this series. The patch series is based on v4.15-rc8. Changes since PATCHv4: * Introduce dsa_port_link_(un)register_of and mark the fixed variant static. * Update patch description to describe the phy<->phy connection from i210 to the Marvell switch Changes since PATCHv3: * Enable the phy in dsa_port_setup() instead of abusing the fixed link setup function Changes since PATCHv2: * Add phy nodes to switch in bx50.dtsi and reference them from switch ports * Enable cpu-port's phy based on 'phy-handle' instead of 'phy-mode' Changes since PATCHv1: * Use 'marvell,mv88e6085' instead of introducing compatible string for mv88e6240. * Fix indention of DT nodes * Only enable 'cpu' phy, if explicitly set to "internal". ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
c89b517da1
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@ -112,3 +112,55 @@
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line-name = "PCA9539-P07";
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};
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};
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&pci_root {
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/* Intel Corporation I210 Gigabit Network Connection */
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switch_nic: ethernet@3,0 {
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compatible = "pci8086,1533";
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reg = <0x00010000 0 0 0 0>;
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};
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};
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&switch_ports {
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port@0 {
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reg = <0>;
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label = "enacq";
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phy-handle = <&switchphy0>;
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};
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port@1 {
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reg = <1>;
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label = "eneport1";
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phy-handle = <&switchphy1>;
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};
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port@2 {
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reg = <2>;
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label = "enix";
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phy-handle = <&switchphy2>;
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};
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port@3 {
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reg = <3>;
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label = "enid";
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phy-handle = <&switchphy3>;
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};
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port@4 {
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reg = <4>;
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label = "cpu";
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ethernet = <&switch_nic>;
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phy-handle = <&switchphy4>;
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};
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port@5 {
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reg = <5>;
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label = "enembc";
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/* connected to Ethernet MAC of AT91RM9200 in MII mode */
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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};
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};
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@ -111,3 +111,55 @@
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fsl,tx-cal-45-dp-ohms = <55>;
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fsl,tx-d-cal = <100>;
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};
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&pci_root {
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/* Intel Corporation I210 Gigabit Network Connection */
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switch_nic: ethernet@3,0 {
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compatible = "pci8086,1533";
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reg = <0x00010000 0 0 0 0>;
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};
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};
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&switch_ports {
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port@0 {
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reg = <0>;
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label = "enacq";
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phy-handle = <&switchphy0>;
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};
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port@1 {
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reg = <1>;
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label = "eneport1";
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phy-handle = <&switchphy1>;
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};
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port@2 {
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reg = <2>;
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label = "enix";
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phy-handle = <&switchphy2>;
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};
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port@3 {
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reg = <3>;
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label = "enid";
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phy-handle = <&switchphy3>;
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};
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port@4 {
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reg = <4>;
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label = "cpu";
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ethernet = <&switch_nic>;
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phy-handle = <&switchphy4>;
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};
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port@5 {
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reg = <5>;
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label = "enembc";
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/* connected to Ethernet MAC of AT91RM9200 in MII mode */
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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};
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};
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@ -212,3 +212,78 @@
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};
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};
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};
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&pci_root {
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/* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */
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bridge@1,0 {
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compatible = "pci10b5,8605";
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reg = <0x00010000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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bridge@2,1 {
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compatible = "pci10b5,8605";
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reg = <0x00020800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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/* Intel Corporation I210 Gigabit Network Connection */
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ethernet@3,0 {
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compatible = "pci8086,1533";
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reg = <0x00030000 0 0 0 0>;
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};
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};
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bridge@2,2 {
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compatible = "pci10b5,8605";
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reg = <0x00021000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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/* Intel Corporation I210 Gigabit Network Connection */
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switch_nic: ethernet@4,0 {
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compatible = "pci8086,1533";
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reg = <0x00040000 0 0 0 0>;
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};
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};
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};
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};
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&switch_ports {
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port@0 {
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reg = <0>;
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label = "eneport1";
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phy-handle = <&switchphy0>;
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};
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port@1 {
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reg = <1>;
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label = "eneport2";
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phy-handle = <&switchphy1>;
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};
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port@2 {
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reg = <2>;
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label = "enix";
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phy-handle = <&switchphy2>;
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};
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port@3 {
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reg = <3>;
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label = "enid";
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phy-handle = <&switchphy3>;
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};
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port@4 {
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reg = <4>;
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label = "cpu";
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ethernet = <&switch_nic>;
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phy-handle = <&switchphy4>;
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};
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};
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@ -92,6 +92,56 @@
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mux-int-port = <1>;
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mux-ext-port = <4>;
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};
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aliases {
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mdio-gpio0 = &mdio0;
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};
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mdio0: mdio-gpio {
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compatible = "virtual,mdio-gpio";
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gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */
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<&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */
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#address-cells = <1>;
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#size-cells = <0>;
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switch@0 {
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compatible = "marvell,mv88e6085"; /* 88e6240*/
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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switch_ports: ports {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switchphy0: switchphy@0 {
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reg = <0>;
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};
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switchphy1: switchphy@1 {
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reg = <1>;
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};
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switchphy2: switchphy@2 {
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reg = <2>;
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};
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switchphy3: switchphy@3 {
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reg = <3>;
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};
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switchphy4: switchphy@4 {
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reg = <4>;
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};
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};
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};
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};
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};
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&ecspi5 {
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tcxo-clock-frequency = <26000000>;
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};
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};
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&pcie {
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/* Synopsys, Inc. Device */
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pci_root: root@0,0 {
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compatible = "pci16c3,abcd";
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reg = <0x00000000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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};
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};
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@ -271,13 +271,12 @@ static int dsa_port_setup(struct dsa_port *dp)
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break;
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case DSA_PORT_TYPE_CPU:
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case DSA_PORT_TYPE_DSA:
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err = dsa_port_fixed_link_register_of(dp);
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err = dsa_port_link_register_of(dp);
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if (err) {
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dev_err(ds->dev, "failed to register fixed link for port %d.%d\n",
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dev_err(ds->dev, "failed to setup link for port %d.%d\n",
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ds->index, dp->index);
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return err;
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}
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break;
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case DSA_PORT_TYPE_USER:
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err = dsa_slave_create(dp);
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@ -301,7 +300,7 @@ static void dsa_port_teardown(struct dsa_port *dp)
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break;
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case DSA_PORT_TYPE_CPU:
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case DSA_PORT_TYPE_DSA:
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dsa_port_fixed_link_unregister_of(dp);
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dsa_port_link_unregister_of(dp);
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break;
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case DSA_PORT_TYPE_USER:
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if (dp->slave) {
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@ -166,8 +166,8 @@ int dsa_port_vlan_add(struct dsa_port *dp,
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struct switchdev_trans *trans);
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int dsa_port_vlan_del(struct dsa_port *dp,
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const struct switchdev_obj_port_vlan *vlan);
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int dsa_port_fixed_link_register_of(struct dsa_port *dp);
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void dsa_port_fixed_link_unregister_of(struct dsa_port *dp);
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int dsa_port_link_register_of(struct dsa_port *dp);
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void dsa_port_link_unregister_of(struct dsa_port *dp);
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/* slave.c */
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extern const struct dsa_device_ops notag_netdev_ops;
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@ -86,7 +86,7 @@ static int dsa_cpu_dsa_setups(struct dsa_switch *ds)
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if (!(dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)))
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continue;
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ret = dsa_port_fixed_link_register_of(&ds->ports[port]);
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ret = dsa_port_link_register_of(&ds->ports[port]);
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if (ret)
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return ret;
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}
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@ -275,7 +275,7 @@ static void dsa_switch_destroy(struct dsa_switch *ds)
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for (port = 0; port < ds->num_ports; port++) {
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if (!(dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)))
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continue;
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dsa_port_fixed_link_unregister_of(&ds->ports[port]);
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dsa_port_link_unregister_of(&ds->ports[port]);
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}
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if (ds->slave_mii_bus && ds->ops->phy_read)
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113
net/dsa/port.c
113
net/dsa/port.c
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@ -273,7 +273,56 @@ int dsa_port_vlan_del(struct dsa_port *dp,
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return 0;
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}
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int dsa_port_fixed_link_register_of(struct dsa_port *dp)
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static int dsa_port_setup_phy_of(struct dsa_port *dp, bool enable)
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{
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struct device_node *port_dn = dp->dn;
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struct device_node *phy_dn;
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struct dsa_switch *ds = dp->ds;
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struct phy_device *phydev;
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int port = dp->index;
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int err = 0;
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phy_dn = of_parse_phandle(port_dn, "phy-handle", 0);
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if (!phy_dn)
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return 0;
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phydev = of_phy_find_device(phy_dn);
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if (!phydev) {
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err = -EPROBE_DEFER;
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goto err_put_of;
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}
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if (enable) {
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err = genphy_config_init(phydev);
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if (err < 0)
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goto err_put_dev;
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err = genphy_resume(phydev);
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if (err < 0)
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goto err_put_dev;
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err = genphy_read_status(phydev);
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if (err < 0)
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goto err_put_dev;
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} else {
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err = genphy_suspend(phydev);
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if (err < 0)
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goto err_put_dev;
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}
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if (ds->ops->adjust_link)
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ds->ops->adjust_link(ds, port, phydev);
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dev_dbg(ds->dev, "enabled port's phy: %s", phydev_name(phydev));
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err_put_dev:
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put_device(&phydev->mdio.dev);
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err_put_of:
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of_node_put(phy_dn);
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return err;
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}
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static int dsa_port_fixed_link_register_of(struct dsa_port *dp)
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{
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struct device_node *dn = dp->dn;
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struct dsa_switch *ds = dp->ds;
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@ -282,38 +331,44 @@ int dsa_port_fixed_link_register_of(struct dsa_port *dp)
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int mode;
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int err;
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if (of_phy_is_fixed_link(dn)) {
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err = of_phy_register_fixed_link(dn);
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if (err) {
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dev_err(ds->dev,
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"failed to register the fixed PHY of port %d\n",
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port);
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return err;
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}
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phydev = of_phy_find_device(dn);
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mode = of_get_phy_mode(dn);
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if (mode < 0)
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mode = PHY_INTERFACE_MODE_NA;
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phydev->interface = mode;
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genphy_config_init(phydev);
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genphy_read_status(phydev);
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if (ds->ops->adjust_link)
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ds->ops->adjust_link(ds, port, phydev);
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put_device(&phydev->mdio.dev);
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err = of_phy_register_fixed_link(dn);
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if (err) {
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dev_err(ds->dev,
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"failed to register the fixed PHY of port %d\n",
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port);
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return err;
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}
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phydev = of_phy_find_device(dn);
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mode = of_get_phy_mode(dn);
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if (mode < 0)
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mode = PHY_INTERFACE_MODE_NA;
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phydev->interface = mode;
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genphy_config_init(phydev);
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genphy_read_status(phydev);
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if (ds->ops->adjust_link)
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ds->ops->adjust_link(ds, port, phydev);
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||||
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||||
put_device(&phydev->mdio.dev);
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return 0;
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||||
}
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||||
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||||
void dsa_port_fixed_link_unregister_of(struct dsa_port *dp)
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||||
int dsa_port_link_register_of(struct dsa_port *dp)
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||||
{
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||||
struct device_node *dn = dp->dn;
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||||
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||||
if (of_phy_is_fixed_link(dn))
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of_phy_deregister_fixed_link(dn);
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||||
if (of_phy_is_fixed_link(dp->dn))
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||||
return dsa_port_fixed_link_register_of(dp);
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||||
else
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||||
return dsa_port_setup_phy_of(dp, true);
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||||
}
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||||
|
||||
void dsa_port_link_unregister_of(struct dsa_port *dp)
|
||||
{
|
||||
if (of_phy_is_fixed_link(dp->dn))
|
||||
of_phy_deregister_fixed_link(dp->dn);
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||||
else
|
||||
dsa_port_setup_phy_of(dp, false);
|
||||
}
|
||||
|
|
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