clk: mediatek: add the option for determining PLL source clock
Since the previous setup always sets the PLL using crystal 26MHz, this doesn't always happen in every MediaTek platform. So the patch added flexibility for assigning extra member for determining the PLL source clock. Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -218,6 +218,7 @@ struct mtk_pll_data {
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uint32_t pcw_reg;
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uint32_t pcw_reg;
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int pcw_shift;
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int pcw_shift;
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const struct mtk_pll_div_table *div_table;
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const struct mtk_pll_div_table *div_table;
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const char *parent_name;
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};
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};
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void mtk_clk_register_plls(struct device_node *node,
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void mtk_clk_register_plls(struct device_node *node,
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@ -312,7 +312,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
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init.name = data->name;
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init.name = data->name;
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init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
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init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
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init.ops = &mtk_pll_ops;
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init.ops = &mtk_pll_ops;
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init.parent_names = &parent_name;
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if (data->parent_name)
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init.parent_names = &data->parent_name;
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else
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.num_parents = 1;
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clk = clk_register(NULL, &pll->hw);
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clk = clk_register(NULL, &pll->hw);
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