reset: imx7: Add support for i.MX8MQ IP block variant
Add bits and pieces needed to support IP block variant found on i.MX8MQ SoCs. Cc: p.zabel@pengutronix.de Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: cphealy@gmail.com Cc: l.stach@pengutronix.de Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> [p.zabel@pengutronix.de: fixed whitespace alignment] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
This commit is contained in:
Andrey Smirnov
Philipp Zabel
parent
1059035853
commit
c979dbf599
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@ -56,9 +56,9 @@ config RESET_HSDK
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This enables the reset controller driver for HSDK board.
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config RESET_IMX7
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bool "i.MX7 Reset Driver" if COMPILE_TEST
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bool "i.MX7/8 Reset Driver" if COMPILE_TEST
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depends on HAS_IOMEM
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default SOC_IMX7D
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default SOC_IMX7D || (ARM64 && ARCH_MXC)
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select MFD_SYSCON
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help
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This enables the reset controller driver for i.MX7 SoCs.
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@ -22,6 +22,7 @@
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#include <linux/reset-controller.h>
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#include <linux/regmap.h>
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#include <dt-bindings/reset/imx7-reset.h>
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#include <dt-bindings/reset/imx8mq-reset.h>
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struct imx7_src_signal {
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unsigned int offset, bit;
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@ -140,6 +141,126 @@ static const struct imx7_src_variant variant_imx7 = {
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},
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};
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enum imx8mq_src_registers {
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SRC_A53RCR0 = 0x0004,
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SRC_HDMI_RCR = 0x0030,
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SRC_DISP_RCR = 0x0034,
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SRC_GPU_RCR = 0x0040,
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SRC_VPU_RCR = 0x0044,
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SRC_PCIE2_RCR = 0x0048,
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SRC_MIPIPHY1_RCR = 0x004c,
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SRC_MIPIPHY2_RCR = 0x0050,
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SRC_DDRC2_RCR = 0x1004,
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};
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static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
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[IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
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[IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
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[IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
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[IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
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[IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
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[IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
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[IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
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[IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
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[IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
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[IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
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[IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
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[IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
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[IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
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[IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
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[IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
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[IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
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[IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
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[IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
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[IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) },
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[IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
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[IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
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[IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) },
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[IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) },
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[IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) },
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[IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) },
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[IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) },
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[IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR,
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BIT(2) | BIT(1) },
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[IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
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[IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
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[IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
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[IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
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[IMX8MQ_RESET_DISP_RESET] = { SRC_DISP_RCR, BIT(0) },
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[IMX8MQ_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
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[IMX8MQ_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
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[IMX8MQ_RESET_PCIEPHY2] = { SRC_PCIE2_RCR,
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BIT(2) | BIT(1) },
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[IMX8MQ_RESET_PCIEPHY2_PERST] = { SRC_PCIE2_RCR, BIT(3) },
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[IMX8MQ_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, BIT(6) },
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[IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, BIT(11) },
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[IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) },
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[IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET] = { SRC_MIPIPHY1_RCR, BIT(1) },
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[IMX8MQ_RESET_MIPI_CSI1_ESC_RESET] = { SRC_MIPIPHY1_RCR, BIT(2) },
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[IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) },
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[IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET] = { SRC_MIPIPHY2_RCR, BIT(1) },
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[IMX8MQ_RESET_MIPI_CSI2_ESC_RESET] = { SRC_MIPIPHY2_RCR, BIT(2) },
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[IMX8MQ_RESET_DDRC1_PRST] = { SRC_DDRC_RCR, BIT(0) },
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[IMX8MQ_RESET_DDRC1_CORE_RESET] = { SRC_DDRC_RCR, BIT(1) },
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[IMX8MQ_RESET_DDRC1_PHY_RESET] = { SRC_DDRC_RCR, BIT(2) },
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[IMX8MQ_RESET_DDRC2_PHY_RESET] = { SRC_DDRC2_RCR, BIT(0) },
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[IMX8MQ_RESET_DDRC2_CORE_RESET] = { SRC_DDRC2_RCR, BIT(1) },
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[IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) },
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};
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static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct imx7_src *imx7src = to_imx7_src(rcdev);
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const unsigned int bit = imx7src->signals[id].bit;
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unsigned int value = assert ? bit : 0;
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switch (id) {
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case IMX8MQ_RESET_PCIEPHY:
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case IMX8MQ_RESET_PCIEPHY2: /* fallthrough */
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/*
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* wait for more than 10us to release phy g_rst and
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* btnrst
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*/
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if (!assert)
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udelay(10);
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break;
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case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
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case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */
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value = assert ? 0 : bit;
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break;
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}
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return imx7_reset_update(imx7src, id, value);
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}
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static int imx8mq_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return imx8mq_reset_set(rcdev, id, true);
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}
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static int imx8mq_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return imx8mq_reset_set(rcdev, id, false);
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}
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static const struct imx7_src_variant variant_imx8mq = {
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.signals = imx8mq_src_signals,
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.signals_num = ARRAY_SIZE(imx8mq_src_signals),
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.ops = {
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.assert = imx8mq_reset_assert,
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.deassert = imx8mq_reset_deassert,
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},
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};
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static int imx7_reset_probe(struct platform_device *pdev)
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{
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struct imx7_src *imx7src;
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@ -169,6 +290,7 @@ static int imx7_reset_probe(struct platform_device *pdev)
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static const struct of_device_id imx7_reset_dt_ids[] = {
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{ .compatible = "fsl,imx7d-src", .data = &variant_imx7 },
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{ .compatible = "fsl,imx8mq-src", .data = &variant_imx8mq },
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{ /* sentinel */ },
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};
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