EDAC, MCE: Add HW_ERR prefix
.. so that the user knows what she's looking at there in dmesg. Also, fix a minor cosmetic output inconsistency. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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ca755e0a49
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c9f281fd96
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@ -133,7 +133,7 @@ static void amd_decode_dc_mce(u64 mc0_status)
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u32 ec = mc0_status & 0xffff;
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u32 ec = mc0_status & 0xffff;
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u32 xec = (mc0_status >> 16) & 0xf;
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u32 xec = (mc0_status >> 16) & 0xf;
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pr_emerg("Data Cache Error");
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pr_emerg(HW_ERR "Data Cache Error: ");
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if (xec == 1 && TLB_ERROR(ec))
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if (xec == 1 && TLB_ERROR(ec))
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pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
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pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
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@ -168,7 +168,7 @@ static void amd_decode_dc_mce(u64 mc0_status)
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return;
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return;
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wrong_dc_mce:
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wrong_dc_mce:
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pr_warning("Corrupted DC MCE info?\n");
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pr_emerg(HW_ERR "Corrupted DC MCE info?\n");
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}
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}
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static void amd_decode_ic_mce(u64 mc1_status)
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static void amd_decode_ic_mce(u64 mc1_status)
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@ -176,7 +176,7 @@ static void amd_decode_ic_mce(u64 mc1_status)
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u32 ec = mc1_status & 0xffff;
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u32 ec = mc1_status & 0xffff;
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u32 xec = (mc1_status >> 16) & 0xf;
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u32 xec = (mc1_status >> 16) & 0xf;
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pr_emerg("Instruction Cache Error");
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pr_emerg(HW_ERR "Instruction Cache Error");
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if (xec == 1 && TLB_ERROR(ec))
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if (xec == 1 && TLB_ERROR(ec))
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pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
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pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
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@ -225,7 +225,7 @@ static void amd_decode_ic_mce(u64 mc1_status)
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return;
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return;
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wrong_ic_mce:
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wrong_ic_mce:
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pr_warning("Corrupted IC MCE info?\n");
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pr_emerg(HW_ERR "Corrupted IC MCE info?\n");
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}
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}
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static void amd_decode_bu_mce(u64 mc2_status)
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static void amd_decode_bu_mce(u64 mc2_status)
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@ -233,7 +233,7 @@ static void amd_decode_bu_mce(u64 mc2_status)
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u32 ec = mc2_status & 0xffff;
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u32 ec = mc2_status & 0xffff;
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u32 xec = (mc2_status >> 16) & 0xf;
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u32 xec = (mc2_status >> 16) & 0xf;
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pr_emerg("Bus Unit Error");
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pr_emerg(HW_ERR "Bus Unit Error");
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if (xec == 0x1)
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if (xec == 0x1)
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pr_cont(" in the write data buffers.\n");
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pr_cont(" in the write data buffers.\n");
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@ -267,7 +267,7 @@ static void amd_decode_bu_mce(u64 mc2_status)
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return;
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return;
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wrong_bu_mce:
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wrong_bu_mce:
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pr_warning("Corrupted BU MCE info?\n");
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pr_emerg(HW_ERR "Corrupted BU MCE info?\n");
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}
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}
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static void amd_decode_ls_mce(u64 mc3_status)
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static void amd_decode_ls_mce(u64 mc3_status)
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@ -275,7 +275,7 @@ static void amd_decode_ls_mce(u64 mc3_status)
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u32 ec = mc3_status & 0xffff;
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u32 ec = mc3_status & 0xffff;
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u32 xec = (mc3_status >> 16) & 0xf;
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u32 xec = (mc3_status >> 16) & 0xf;
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pr_emerg("Load Store Error");
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pr_emerg(HW_ERR "Load Store Error");
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if (xec == 0x0) {
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if (xec == 0x0) {
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u8 rrrr = (ec >> 4) & 0xf;
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u8 rrrr = (ec >> 4) & 0xf;
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@ -288,7 +288,7 @@ static void amd_decode_ls_mce(u64 mc3_status)
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return;
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return;
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wrong_ls_mce:
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wrong_ls_mce:
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pr_warning("Corrupted LS MCE info?\n");
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pr_emerg(HW_ERR "Corrupted LS MCE info?\n");
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}
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}
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void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
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void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
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@ -304,7 +304,7 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
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if (TLB_ERROR(ec) && !report_gart_errors)
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if (TLB_ERROR(ec) && !report_gart_errors)
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return;
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return;
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pr_emerg("Northbridge Error, node %d", node_id);
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pr_emerg(HW_ERR "Northbridge Error, node %d", node_id);
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/*
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/*
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* F10h, revD can disable ErrCpu[3:0] so check that first and also the
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* F10h, revD can disable ErrCpu[3:0] so check that first and also the
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@ -323,7 +323,7 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
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pr_cont("\n");
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pr_cont("\n");
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}
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}
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pr_emerg("%s.\n", EXT_ERR_MSG(regs->nbsl));
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pr_emerg(HW_ERR "%s.\n", EXT_ERR_MSG(regs->nbsl));
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if (BUS_ERROR(ec) && nb_bus_decoder)
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if (BUS_ERROR(ec) && nb_bus_decoder)
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nb_bus_decoder(node_id, regs);
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nb_bus_decoder(node_id, regs);
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@ -334,26 +334,26 @@ static void amd_decode_fr_mce(u64 mc5_status)
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{
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{
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/* we have only one error signature so match all fields at once. */
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/* we have only one error signature so match all fields at once. */
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if ((mc5_status & 0xffff) == 0x0f0f)
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if ((mc5_status & 0xffff) == 0x0f0f)
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pr_emerg(" FR Error: CPU Watchdog timer expire.\n");
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pr_emerg(HW_ERR " FR Error: CPU Watchdog timer expire.\n");
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else
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else
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pr_warning("Corrupted FR MCE info?\n");
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pr_emerg(HW_ERR "Corrupted FR MCE info?\n");
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}
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}
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static inline void amd_decode_err_code(unsigned int ec)
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static inline void amd_decode_err_code(unsigned int ec)
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{
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{
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if (TLB_ERROR(ec)) {
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if (TLB_ERROR(ec)) {
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pr_emerg("Transaction: %s, Cache Level %s\n",
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pr_emerg(HW_ERR "Transaction: %s, Cache Level: %s\n",
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TT_MSG(ec), LL_MSG(ec));
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TT_MSG(ec), LL_MSG(ec));
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} else if (MEM_ERROR(ec)) {
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} else if (MEM_ERROR(ec)) {
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pr_emerg("Transaction: %s, Type: %s, Cache Level: %s",
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pr_emerg(HW_ERR "Transaction: %s, Type: %s, Cache Level: %s",
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RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
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RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
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} else if (BUS_ERROR(ec)) {
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} else if (BUS_ERROR(ec)) {
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pr_emerg("Transaction type: %s(%s), %s, Cache Level: %s, "
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pr_emerg(HW_ERR "Transaction type: %s(%s), %s, Cache Level: %s, "
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"Participating Processor: %s\n",
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"Participating Processor: %s\n",
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RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec),
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RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec),
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PP_MSG(ec));
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PP_MSG(ec));
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} else
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} else
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pr_warning("Huh? Unknown MCE error 0x%x\n", ec);
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pr_emerg(HW_ERR "Huh? Unknown MCE error 0x%x\n", ec);
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}
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}
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static int amd_decode_mce(struct notifier_block *nb, unsigned long val,
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static int amd_decode_mce(struct notifier_block *nb, unsigned long val,
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@ -363,7 +363,7 @@ static int amd_decode_mce(struct notifier_block *nb, unsigned long val,
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struct err_regs regs;
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struct err_regs regs;
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int node, ecc;
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int node, ecc;
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pr_emerg("MC%d_STATUS: ", m->bank);
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pr_emerg(HW_ERR "MC%d_STATUS: ", m->bank);
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pr_cont("%sorrected error, other errors lost: %s, "
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pr_cont("%sorrected error, other errors lost: %s, "
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"CPU context corrupt: %s",
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"CPU context corrupt: %s",
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