bnx2x: Fix BCM57810-KR FC
Fix 57810-KR flow-control handling link is achieved via CL37 AN. Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -3655,6 +3655,33 @@ static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
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if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
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bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
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bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
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} else if (CHIP_IS_E3(bp) &&
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SINGLE_MEDIA_DIRECT(params)) {
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u8 lane = bnx2x_get_warpcore_lane(phy, params);
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u16 gp_status, gp_mask;
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bnx2x_cl45_read(bp, phy,
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MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
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&gp_status);
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gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
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MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
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lane;
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if ((gp_status & gp_mask) == gp_mask) {
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bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
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MDIO_AN_REG_ADV_PAUSE, &ld_pause);
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bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
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MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
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} else {
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bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
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MDIO_AN_REG_CL37_FC_LD, &ld_pause);
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bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
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MDIO_AN_REG_CL37_FC_LP, &lp_pause);
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ld_pause = ((ld_pause &
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MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
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<< 3);
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lp_pause = ((lp_pause &
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MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
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<< 3);
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}
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} else {
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bnx2x_cl45_read(bp, phy,
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MDIO_AN_DEVAD,
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@ -6944,6 +6944,10 @@ Theotherbitsarereservedandshouldbezero*/
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#define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
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#define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
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#define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
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#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
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#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
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#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
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#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
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#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
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#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
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#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
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