drm/nva3/pm: rewrite clock_set, and switch to new interfaces
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
77e7da6814
commit
ca94a71fc4
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@ -59,10 +59,9 @@ void *nv50_pm_clock_pre(struct drm_device *, struct nouveau_pm_level *,
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void nv50_pm_clock_set(struct drm_device *, void *);
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/* nva3_pm.c */
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int nva3_pm_clock_get(struct drm_device *, u32 id);
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void *nva3_pm_clock_pre(struct drm_device *, struct nouveau_pm_level *,
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u32 id, int khz);
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void nva3_pm_clock_set(struct drm_device *, void *);
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int nva3_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *);
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void *nva3_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *);
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void nva3_pm_clocks_set(struct drm_device *, void *);
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/* nouveau_temp.c */
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void nouveau_temp_init(struct drm_device *dev);
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@ -359,9 +359,9 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->pm.clock_set = nv50_pm_clock_set;
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break;
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default:
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engine->pm.clock_get = nva3_pm_clock_get;
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engine->pm.clock_pre = nva3_pm_clock_pre;
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engine->pm.clock_set = nva3_pm_clock_set;
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engine->pm.clocks_get = nva3_pm_clocks_get;
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engine->pm.clocks_pre = nva3_pm_clocks_pre;
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engine->pm.clocks_set = nva3_pm_clocks_set;
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break;
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}
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engine->pm.voltage_get = nouveau_voltage_gpio_get;
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@ -27,11 +27,20 @@
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#include "nouveau_bios.h"
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#include "nouveau_pm.h"
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static u32 read_pll(struct drm_device *dev, u32 pll, int clk);
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static u32 read_clk(struct drm_device *dev, int clk);
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static u32 read_clk(struct drm_device *, int, bool);
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static u32 read_pll(struct drm_device *, u32, int);
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static u32
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read_clk(struct drm_device *dev, int clk)
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read_vco(struct drm_device *dev, int clk)
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{
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u32 sctl = nv_rd32(dev, 0x4120 + (clk * 4));
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if ((sctl & 0x00000030) != 0x00000030)
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return read_pll(dev, 0x00e820, 0x41);
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return read_pll(dev, 0x00e8a0, 0x42);
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}
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static u32
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read_clk(struct drm_device *dev, int clk, bool ignore_en)
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{
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u32 sctl, sdiv, sclk;
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@ -39,20 +48,19 @@ read_clk(struct drm_device *dev, int clk)
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return 27000;
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sctl = nv_rd32(dev, 0x4120 + (clk * 4));
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switch (sctl & 0x00003100) {
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case 0x00000100:
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if (!ignore_en && !(sctl & 0x00000100))
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return 0;
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switch (sctl & 0x00003000) {
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case 0x00000000:
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return 27000;
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case 0x00002100:
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case 0x00002000:
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if (sctl & 0x00000040)
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return 108000;
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return 100000;
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case 0x00003100:
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case 0x00003000:
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sclk = read_vco(dev, clk);
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sdiv = ((sctl & 0x003f0000) >> 16) + 2;
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if ((sctl & 0x00000030) != 0x00000030)
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sclk = read_pll(dev, 0x00e820, 0x41);
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else
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sclk = read_pll(dev, 0x00e8a0, 0x42);
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return (sclk * 2) / sdiv;
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default:
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return 0;
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@ -73,161 +81,158 @@ read_pll(struct drm_device *dev, u32 pll, int clk)
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if ((pll & 0x00ff00) == 0x00e800)
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P = 1;
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sclk = read_clk(dev, 0x00 + clk);
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sclk = read_clk(dev, 0x00 + clk, false);
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} else {
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sclk = read_clk(dev, 0x10 + clk);
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sclk = read_clk(dev, 0x10 + clk, false);
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}
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return sclk * N / (M * P);
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}
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struct nva3_pm_state {
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enum pll_types type;
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u32 src0;
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u32 src1;
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u32 ctrl;
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u32 coef;
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u32 old_pnm;
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u32 new_pnm;
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u32 new_div;
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struct creg {
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u32 clk;
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u32 pll;
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};
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static int
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nva3_pm_pll_offset(u32 id)
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calc_clk(struct drm_device *dev, u32 pll, int clk, u32 khz, struct creg *reg)
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{
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static const u32 pll_map[] = {
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0x00, PLL_CORE,
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0x01, PLL_SHADER,
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0x02, PLL_MEMORY,
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0x00, 0x00
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};
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const u32 *map = pll_map;
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struct pll_lims limits;
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u32 oclk, sclk, sdiv;
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int P, N, M, diff;
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int ret;
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while (map[1]) {
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if (id == map[1])
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return map[0];
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map += 2;
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reg->pll = 0;
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reg->clk = 0;
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switch (khz) {
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case 27000:
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reg->clk = 0x00000100;
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return khz;
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case 100000:
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reg->clk = 0x00002100;
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return khz;
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case 108000:
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reg->clk = 0x00002140;
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return khz;
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default:
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sclk = read_vco(dev, clk);
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sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
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if (sdiv > 4) {
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oclk = (sclk * 2) / sdiv;
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diff = khz - oclk;
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if (!pll || (diff >= -2000 && diff < 3000)) {
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reg->clk = (((sdiv - 2) << 16) | 0x00003100);
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return oclk;
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}
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}
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break;
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}
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return -ENOENT;
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ret = get_pll_limits(dev, pll, &limits);
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if (ret)
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return ret;
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limits.refclk = read_clk(dev, clk - 0x10, true);
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if (!limits.refclk)
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return -EINVAL;
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ret = nva3_calc_pll(dev, &limits, khz, &N, NULL, &M, &P);
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if (ret >= 0) {
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reg->clk = nv_rd32(dev, 0x4120 + (clk * 4));
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reg->pll = (P << 16) | (N << 8) | M;
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}
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return ret;
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}
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int
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nva3_pm_clock_get(struct drm_device *dev, u32 id)
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nva3_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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{
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switch (id) {
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case PLL_CORE:
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return read_pll(dev, 0x4200, 0);
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case PLL_SHADER:
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return read_pll(dev, 0x4220, 1);
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case PLL_MEMORY:
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return read_pll(dev, 0x4000, 2);
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default:
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return -ENOENT;
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}
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perflvl->core = read_pll(dev, 0x4200, 0);
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perflvl->shader = read_pll(dev, 0x4220, 1);
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perflvl->memory = read_pll(dev, 0x4000, 2);
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return 0;
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}
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struct nva3_pm_state {
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struct creg nclk;
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struct creg sclk;
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struct creg mclk;
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};
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void *
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nva3_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl,
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u32 id, int khz)
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nva3_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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{
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struct nva3_pm_state *pll;
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struct pll_lims limits;
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int N, M, P, diff;
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int ret, off;
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struct nva3_pm_state *info;
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int ret;
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ret = get_pll_limits(dev, id, &limits);
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if (ret < 0)
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return (ret == -ENOENT) ? NULL : ERR_PTR(ret);
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off = nva3_pm_pll_offset(id);
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if (id < 0)
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return ERR_PTR(-EINVAL);
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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info = kzalloc(sizeof(*info), GFP_KERNEL);
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if (!info)
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return ERR_PTR(-ENOMEM);
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pll->type = id;
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pll->src0 = 0x004120 + (off * 4);
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pll->src1 = 0x004160 + (off * 4);
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pll->ctrl = limits.reg + 0;
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pll->coef = limits.reg + 4;
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/* If target clock is within [-2, 3) MHz of a divisor, we'll
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* use that instead of calculating MNP values
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*/
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pll->new_div = min((limits.refclk * 2) / (khz - 2999), 16);
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if (pll->new_div) {
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diff = khz - ((limits.refclk * 2) / pll->new_div);
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if (diff < -2000 || diff >= 3000)
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pll->new_div = 0;
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ret = calc_clk(dev, 0x4200, 0x10, perflvl->core, &info->nclk);
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if (ret < 0)
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goto out;
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ret = calc_clk(dev, 0x4220, 0x11, perflvl->shader, &info->sclk);
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if (ret < 0)
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goto out;
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ret = calc_clk(dev, 0x4000, 0x12, perflvl->memory, &info->mclk);
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if (ret < 0)
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goto out;
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out:
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if (ret < 0) {
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kfree(info);
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info = ERR_PTR(ret);
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}
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return info;
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}
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if (!pll->new_div) {
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ret = nva3_calc_pll(dev, &limits, khz, &N, NULL, &M, &P);
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if (ret < 0)
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return ERR_PTR(ret);
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static void
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prog_pll(struct drm_device *dev, u32 pll, int clk, struct creg *reg)
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{
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const u32 src0 = 0x004120 + (clk * 4);
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const u32 src1 = 0x004160 + (clk * 4);
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const u32 ctrl = pll + 0;
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const u32 coef = pll + 4;
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u32 cntl;
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pll->new_pnm = (P << 16) | (N << 8) | M;
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pll->new_div = 2 - 1;
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cntl = nv_rd32(dev, ctrl) & 0xfffffff2;
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if (reg->pll) {
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nv_mask(dev, src0, 0x00000101, 0x00000101);
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nv_wr32(dev, coef, reg->pll);
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nv_wr32(dev, ctrl, cntl | 0x00000015);
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nv_mask(dev, src1, 0x00000100, 0x00000000);
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nv_mask(dev, src1, 0x00000001, 0x00000000);
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} else {
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pll->new_pnm = 0;
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pll->new_div--;
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nv_mask(dev, src1, 0x003f3141, 0x00000101 | reg->clk);
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nv_wr32(dev, ctrl, cntl | 0x0000001d);
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nv_mask(dev, ctrl, 0x00000001, 0x00000000);
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nv_mask(dev, src0, 0x00000100, 0x00000000);
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nv_mask(dev, src0, 0x00000001, 0x00000000);
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}
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if ((nv_rd32(dev, pll->src1) & 0x00000101) != 0x00000101)
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pll->old_pnm = nv_rd32(dev, pll->coef);
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return pll;
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}
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void
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nva3_pm_clock_set(struct drm_device *dev, void *pre_state)
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nva3_pm_clocks_set(struct drm_device *dev, void *pre_state)
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{
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struct nva3_pm_state *pll = pre_state;
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u32 ctrl = 0;
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struct nva3_pm_state *info = pre_state;
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/* For the memory clock, NVIDIA will build a "script" describing
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* the reclocking process and ask PDAEMON to execute it.
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*/
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if (pll->type == PLL_MEMORY) {
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nv_wr32(dev, 0x100210, 0);
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nv_wr32(dev, 0x1002dc, 1);
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nv_wr32(dev, 0x004018, 0x00001000);
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ctrl = 0x18000100;
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}
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prog_pll(dev, 0x004200, 0, &info->nclk);
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prog_pll(dev, 0x004220, 1, &info->sclk);
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if (pll->old_pnm || !pll->new_pnm) {
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nv_mask(dev, pll->src1, 0x003c0101, 0x00000101 |
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(pll->new_div << 18));
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nv_wr32(dev, pll->ctrl, 0x0001001d | ctrl);
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nv_mask(dev, pll->ctrl, 0x00000001, 0x00000000);
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}
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nv_wr32(dev, 0x100210, 0);
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nv_wr32(dev, 0x1002dc, 1);
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nv_wr32(dev, 0x004018, 0x00001000);
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prog_pll(dev, 0x004000, 2, &info->mclk);
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if (nv_rd32(dev, 0x4000) & 0x00000008)
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nv_wr32(dev, 0x004018, 0x1000d000);
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else
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nv_wr32(dev, 0x004018, 0x10005000);
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nv_wr32(dev, 0x1002dc, 0);
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nv_wr32(dev, 0x100210, 0x80000000);
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if (pll->new_pnm) {
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nv_mask(dev, pll->src0, 0x00000101, 0x00000101);
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nv_wr32(dev, pll->coef, pll->new_pnm);
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nv_wr32(dev, pll->ctrl, 0x0001001d | ctrl);
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nv_mask(dev, pll->ctrl, 0x00000010, 0x00000000);
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nv_mask(dev, pll->ctrl, 0x00020010, 0x00020010);
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nv_wr32(dev, pll->ctrl, 0x00010015 | ctrl);
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nv_mask(dev, pll->src1, 0x00000100, 0x00000000);
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nv_mask(dev, pll->src1, 0x00000001, 0x00000000);
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if (pll->type == PLL_MEMORY)
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nv_wr32(dev, 0x4018, 0x10005000);
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} else {
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nv_mask(dev, pll->ctrl, 0x00000001, 0x00000000);
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nv_mask(dev, pll->src0, 0x00000100, 0x00000000);
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nv_mask(dev, pll->src0, 0x00000001, 0x00000000);
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if (pll->type == PLL_MEMORY)
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nv_wr32(dev, 0x4018, 0x1000d000);
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}
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if (pll->type == PLL_MEMORY) {
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nv_wr32(dev, 0x1002dc, 0);
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nv_wr32(dev, 0x100210, 0x80000000);
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}
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kfree(pll);
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kfree(info);
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}
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