x86, cacheinfo: Enable L3 CID only on AMD
Final stage linking can fail with arch/x86/built-in.o: In function `store_cache_disable': intel_cacheinfo.c:(.text+0xc509): undefined reference to `amd_get_nb_id' arch/x86/built-in.o: In function `show_cache_disable': intel_cacheinfo.c:(.text+0xc7d3): undefined reference to `amd_get_nb_id' when CONFIG_CPU_SUP_AMD is not enabled because the amd_get_nb_id helper is defined in AMD-specific code but also used in generic code (intel_cacheinfo.c). Reorganize the L3 cache index disable code under CONFIG_CPU_SUP_AMD since it is AMD-only anyway. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> LKML-Reference: <20100218184210.GF20473@aftab> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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@ -293,6 +293,13 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
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(ebx->split.ways_of_associativity + 1) - 1;
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}
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struct _cache_attr {
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struct attribute attr;
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ssize_t (*show)(struct _cpuid4_info *, char *);
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ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
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};
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#ifdef CONFIG_CPU_SUP_AMD
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static unsigned int __cpuinit amd_calc_l3_indices(void)
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{
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/*
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@ -303,7 +310,7 @@ static unsigned int __cpuinit amd_calc_l3_indices(void)
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int node = cpu_to_node(cpu);
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struct pci_dev *dev = node_to_k8_nb_misc(node);
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unsigned int sc0, sc1, sc2, sc3;
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u32 val;
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u32 val = 0;
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pci_read_config_dword(dev, 0x1C4, &val);
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@ -335,6 +342,94 @@ amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
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this_leaf->l3_indices = amd_calc_l3_indices();
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}
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static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
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unsigned int index)
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{
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int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
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int node = amd_get_nb_id(cpu);
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struct pci_dev *dev = node_to_k8_nb_misc(node);
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unsigned int reg = 0;
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if (!this_leaf->can_disable)
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return -EINVAL;
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if (!dev)
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return -EINVAL;
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pci_read_config_dword(dev, 0x1BC + index * 4, ®);
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return sprintf(buf, "0x%08x\n", reg);
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}
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#define SHOW_CACHE_DISABLE(index) \
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static ssize_t \
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show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf) \
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{ \
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return show_cache_disable(this_leaf, buf, index); \
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}
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SHOW_CACHE_DISABLE(0)
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SHOW_CACHE_DISABLE(1)
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static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
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const char *buf, size_t count, unsigned int index)
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{
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int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
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int node = amd_get_nb_id(cpu);
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struct pci_dev *dev = node_to_k8_nb_misc(node);
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unsigned long val = 0;
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#define SUBCACHE_MASK (3UL << 20)
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#define SUBCACHE_INDEX 0xfff
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if (!this_leaf->can_disable)
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return -EINVAL;
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if (!capable(CAP_SYS_ADMIN))
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return -EPERM;
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if (!dev)
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return -EINVAL;
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if (strict_strtoul(buf, 10, &val) < 0)
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return -EINVAL;
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/* do not allow writes outside of allowed bits */
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if ((val & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||
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((val & SUBCACHE_INDEX) > this_leaf->l3_indices))
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return -EINVAL;
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val |= BIT(30);
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pci_write_config_dword(dev, 0x1BC + index * 4, val);
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/*
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* We need to WBINVD on a core on the node containing the L3 cache which
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* indices we disable therefore a simple wbinvd() is not sufficient.
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*/
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wbinvd_on_cpu(cpu);
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pci_write_config_dword(dev, 0x1BC + index * 4, val | BIT(31));
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return count;
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}
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#define STORE_CACHE_DISABLE(index) \
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static ssize_t \
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store_cache_disable_##index(struct _cpuid4_info *this_leaf, \
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const char *buf, size_t count) \
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{ \
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return store_cache_disable(this_leaf, buf, count, index); \
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}
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STORE_CACHE_DISABLE(0)
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STORE_CACHE_DISABLE(1)
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static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
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show_cache_disable_0, store_cache_disable_0);
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static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
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show_cache_disable_1, store_cache_disable_1);
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#else /* CONFIG_CPU_SUP_AMD */
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static void __cpuinit
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amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
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{
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};
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#endif /* CONFIG_CPU_SUP_AMD */
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static int
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__cpuinit cpuid4_cache_lookup_regs(int index,
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struct _cpuid4_info_regs *this_leaf)
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@ -740,88 +835,6 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
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#define to_object(k) container_of(k, struct _index_kobject, kobj)
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#define to_attr(a) container_of(a, struct _cache_attr, attr)
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static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
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unsigned int index)
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{
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int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
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int node = amd_get_nb_id(cpu);
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struct pci_dev *dev = node_to_k8_nb_misc(node);
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unsigned int reg = 0;
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if (!this_leaf->can_disable)
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return -EINVAL;
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if (!dev)
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return -EINVAL;
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pci_read_config_dword(dev, 0x1BC + index * 4, ®);
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return sprintf(buf, "0x%08x\n", reg);
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}
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#define SHOW_CACHE_DISABLE(index) \
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static ssize_t \
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show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf) \
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{ \
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return show_cache_disable(this_leaf, buf, index); \
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}
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SHOW_CACHE_DISABLE(0)
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SHOW_CACHE_DISABLE(1)
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static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
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const char *buf, size_t count, unsigned int index)
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{
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int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
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int node = amd_get_nb_id(cpu);
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struct pci_dev *dev = node_to_k8_nb_misc(node);
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unsigned long val = 0;
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#define SUBCACHE_MASK (3UL << 20)
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#define SUBCACHE_INDEX 0xfff
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if (!this_leaf->can_disable)
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return -EINVAL;
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if (!capable(CAP_SYS_ADMIN))
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return -EPERM;
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if (!dev)
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return -EINVAL;
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if (strict_strtoul(buf, 10, &val) < 0)
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return -EINVAL;
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/* do not allow writes outside of allowed bits */
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if ((val & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||
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((val & SUBCACHE_INDEX) > this_leaf->l3_indices))
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return -EINVAL;
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val |= BIT(30);
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pci_write_config_dword(dev, 0x1BC + index * 4, val);
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/*
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* We need to WBINVD on a core on the node containing the L3 cache which
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* indices we disable therefore a simple wbinvd() is not sufficient.
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*/
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wbinvd_on_cpu(cpu);
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pci_write_config_dword(dev, 0x1BC + index * 4, val | BIT(31));
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return count;
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}
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#define STORE_CACHE_DISABLE(index) \
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static ssize_t \
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store_cache_disable_##index(struct _cpuid4_info *this_leaf, \
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const char *buf, size_t count) \
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{ \
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return store_cache_disable(this_leaf, buf, count, index); \
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}
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STORE_CACHE_DISABLE(0)
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STORE_CACHE_DISABLE(1)
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struct _cache_attr {
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struct attribute attr;
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ssize_t (*show)(struct _cpuid4_info *, char *);
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ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
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};
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#define define_one_ro(_name) \
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static struct _cache_attr _name = \
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__ATTR(_name, 0444, show_##_name, NULL)
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define_one_ro(shared_cpu_map);
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define_one_ro(shared_cpu_list);
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static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
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show_cache_disable_0, store_cache_disable_0);
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static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
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show_cache_disable_1, store_cache_disable_1);
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#define DEFAULT_SYSFS_CACHE_ATTRS \
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&type.attr, \
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&level.attr, \
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static struct attribute *default_l3_attrs[] = {
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DEFAULT_SYSFS_CACHE_ATTRS,
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#ifdef CONFIG_CPU_SUP_AMD
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&cache_disable_0.attr,
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&cache_disable_1.attr,
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#endif
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NULL
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};
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