amd64_edac: Cleanup Dram Configuration registers handling
* Restrict DCT ganged mode check since only Fam10h supports it * Adjust DRAM type detection for BD since it only supports DDR3 * Remove second and thus unneeded DCLR read in k8_early_channel_count() - we do that in read_mc_regs() * Cleanup comments and remove family names from register macros * Remove unused defines There should be no functional change resulting from this patch. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Borislav Petkov
parent
525a1b20a6
commit
cb32850744
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@ -799,7 +799,7 @@ static u16 extract_syndrome(struct err_regs *err)
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*/
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static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt)
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{
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int bit;
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u8 bit;
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enum dev_type edac_cap = EDAC_FLAG_NONE;
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bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= K8_REV_F)
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@ -826,8 +826,9 @@ static void amd64_dump_dramcfg_low(u32 dclr, int chan)
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debugf1(" PAR/ERR parity: %s\n",
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(dclr & BIT(8)) ? "enabled" : "disabled");
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debugf1(" DCT 128bit mode width: %s\n",
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(dclr & BIT(11)) ? "128b" : "64b");
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if (boot_cpu_data.x86 == 0x10)
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debugf1(" DCT 128bit mode width: %s\n",
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(dclr & BIT(11)) ? "128b" : "64b");
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debugf1(" x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
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(dclr & BIT(12)) ? "yes" : "no",
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@ -939,7 +940,10 @@ static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt, int cs)
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{
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enum mem_type type;
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if (boot_cpu_data.x86 >= 0x10 || pvt->ext_model >= K8_REV_F) {
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/* F15h supports only DDR3 */
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if (boot_cpu_data.x86 >= 0x15)
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type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3;
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else if (boot_cpu_data.x86 == 0x10 || pvt->ext_model >= K8_REV_F) {
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if (pvt->dchr0 & DDR3_MODE)
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type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3;
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else
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@ -953,22 +957,10 @@ static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt, int cs)
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return type;
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}
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/*
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* Read the DRAM Configuration Low register. It differs between CG, D & E revs
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* and the later RevF memory controllers (DDR vs DDR2)
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*
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* Return:
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* number of memory channels in operation
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* Pass back:
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* contents of the DCL0_LOW register
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*/
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/* Get the number of DCT channels the memory controller is using. */
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static int k8_early_channel_count(struct amd64_pvt *pvt)
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{
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int flag, err = 0;
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err = amd64_read_dct_pci_cfg(pvt, F10_DCLR_0, &pvt->dclr0);
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if (err)
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return err;
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int flag;
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if (pvt->ext_model >= K8_REV_F)
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/* RevF (NPT) and later */
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@ -983,7 +975,7 @@ static int k8_early_channel_count(struct amd64_pvt *pvt)
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return (flag) ? 2 : 1;
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}
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/* extract the ERROR ADDRESS for the K8 CPUs */
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/* Extract the ERROR ADDRESS for the K8 CPUs */
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static u64 k8_get_error_address(struct mem_ctl_info *mci,
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struct err_regs *info)
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{
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@ -1486,7 +1478,7 @@ static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
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/*
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* debug routine to display the memory sizes of all logical DIMMs and its
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* CSROWs as well
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* CSROWs
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*/
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static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt)
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{
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@ -1960,12 +1952,12 @@ static void read_mc_regs(struct amd64_pvt *pvt)
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amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare);
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amd64_read_dct_pci_cfg(pvt, F10_DCLR_0, &pvt->dclr0);
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amd64_read_dct_pci_cfg(pvt, F10_DCHR_0, &pvt->dchr0);
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amd64_read_dct_pci_cfg(pvt, DCLR0, &pvt->dclr0);
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amd64_read_dct_pci_cfg(pvt, DCHR0, &pvt->dchr0);
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if (!dct_ganging_enabled(pvt)) {
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amd64_read_dct_pci_cfg(pvt, F10_DCLR_1, &pvt->dclr1);
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amd64_read_dct_pci_cfg(pvt, F10_DCHR_1, &pvt->dchr1);
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if (!dct_ganging_enabled(pvt) && boot_cpu_data.x86 > 0xf) {
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amd64_read_dct_pci_cfg(pvt, DCLR1, &pvt->dclr1);
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amd64_read_dct_pci_cfg(pvt, DCHR1, &pvt->dchr1);
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}
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if (boot_cpu_data.x86 >= 0x10) {
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@ -218,27 +218,23 @@
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#define DBAM_MAX_VALUE 11
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#define F10_DCLR_0 0x90
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#define F10_DCLR_1 0x190
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#define DCLR0 0x90
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#define DCLR1 0x190
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#define REVE_WIDTH_128 BIT(16)
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#define F10_WIDTH_128 BIT(11)
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#define F10_DCHR_0 0x94
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#define F10_DCHR_1 0x194
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#define F10_DCHR_FOUR_RANK_DIMM BIT(18)
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#define DCHR0 0x94
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#define DCHR1 0x194
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#define DDR3_MODE BIT(8)
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#define F10_DCHR_MblMode BIT(6)
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#define F10_DCTL_SEL_LOW 0x110
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#define dct_sel_baseaddr(pvt) ((pvt->dct_sel_low) & 0xFFFFF800)
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#define dct_sel_interleave_addr(pvt) (((pvt->dct_sel_low) >> 6) & 0x3)
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#define dct_high_range_enabled(pvt) (pvt->dct_sel_low & BIT(0))
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#define dct_interleave_enabled(pvt) (pvt->dct_sel_low & BIT(2))
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#define dct_ganging_enabled(pvt) (pvt->dct_sel_low & BIT(4))
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#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_low & BIT(4)))
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#define dct_data_intlv_enabled(pvt) (pvt->dct_sel_low & BIT(5))
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#define dct_dram_enabled(pvt) (pvt->dct_sel_low & BIT(8))
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#define dct_memory_cleared(pvt) (pvt->dct_sel_low & BIT(10))
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@ -262,7 +258,6 @@
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#define K8_NBSL 0x48
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/* Family F10h: Normalized Extended Error Codes */
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#define F10_NBSL_EXT_ERR_RES 0x0
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#define F10_NBSL_EXT_ERR_ECC 0x8
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