sh: Renesas R0P7785LC0011RL board support
This adds initial support for the Renesas R0P7785LC0011RL board. This patch supports 29bit address mode only. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Yoshihiro Shimoda
Paul Mundt
parent
1eca5c9272
commit
cbe9da029d
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@ -495,6 +495,21 @@ config SH_HIGHLANDER
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select SYS_SUPPORTS_PCI
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select IO_TRAPPED
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config SH_SH7785LCR
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bool "SH7785LCR"
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depends on CPU_SUBTYPE_SH7785
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select SYS_SUPPORTS_PCI
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select IO_TRAPPED
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config SH_SH7785LCR_29BIT_PHYSMAPS
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bool "SH7785LCR 29bit physmaps"
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depends on SH_SH7785LCR
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default y
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help
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This board has 2 physical memory maps. It can be changed with
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DIP switch(S2-5). If you set the DIP switch for S2-5 = ON,
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you can access all on-board device in 29bit address mode.
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config SH_MIGOR
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bool "Migo-R"
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depends on CPU_SUBTYPE_SH7722
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@ -124,6 +124,7 @@ machdir-$(CONFIG_SH_X3PROTO) += renesas/x3proto
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machdir-$(CONFIG_SH_RSK7203) += renesas/rsk7203
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machdir-$(CONFIG_SH_AP325RXA) += renesas/ap325rxa
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machdir-$(CONFIG_SH_SH7763RDP) += renesas/sh7763rdp
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machdir-$(CONFIG_SH_SH7785LCR) += renesas/sh7785lcr
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machdir-$(CONFIG_SH_SH4202_MICRODEV) += superh/microdev
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machdir-$(CONFIG_SH_LANDISK) += landisk
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machdir-$(CONFIG_SH_TITAN) += titan
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@ -0,0 +1 @@
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obj-y := setup.o
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@ -0,0 +1,302 @@
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/*
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* Renesas Technology Corp. R0P7785LC0011RL Support.
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*
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* Copyright (C) 2008 Yoshihiro Shimoda
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/sm501.h>
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#include <linux/sm501-regs.h>
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#include <linux/fb.h>
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#include <linux/mtd/physmap.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/i2c-pca-platform.h>
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#include <linux/i2c-algo-pca.h>
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#include <asm/heartbeat.h>
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#include <asm/sh7785lcr.h>
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/*
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* NOTE: This board has 2 physical memory maps.
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* Please look at include/asm-sh/sh7785lcr.h or hardware manual.
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*/
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static struct resource heartbeat_resources[] = {
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[0] = {
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.start = PLD_LEDCR,
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.end = PLD_LEDCR,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct heartbeat_data heartbeat_data = {
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.regsize = 8,
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};
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static struct platform_device heartbeat_device = {
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.name = "heartbeat",
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.id = -1,
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.dev = {
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.platform_data = &heartbeat_data,
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},
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.num_resources = ARRAY_SIZE(heartbeat_resources),
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.resource = heartbeat_resources,
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};
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static struct mtd_partition nor_flash_partitions[] = {
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{
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.name = "loader",
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.offset = 0x00000000,
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.size = 512 * 1024,
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},
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{
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.name = "bootenv",
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.offset = MTDPART_OFS_APPEND,
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.size = 512 * 1024,
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},
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{
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.name = "kernel",
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.offset = MTDPART_OFS_APPEND,
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.size = 4 * 1024 * 1024,
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},
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{
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.name = "data",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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},
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};
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static struct physmap_flash_data nor_flash_data = {
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.width = 4,
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.parts = nor_flash_partitions,
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.nr_parts = ARRAY_SIZE(nor_flash_partitions),
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};
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static struct resource nor_flash_resources[] = {
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[0] = {
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.start = NOR_FLASH_ADDR,
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.end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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static struct platform_device nor_flash_device = {
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.name = "physmap-flash",
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.dev = {
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.platform_data = &nor_flash_data,
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},
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.num_resources = ARRAY_SIZE(nor_flash_resources),
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.resource = nor_flash_resources,
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};
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static struct resource r8a66597_usb_host_resources[] = {
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[0] = {
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.name = "r8a66597_hcd",
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.start = R8A66597_ADDR,
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.end = R8A66597_ADDR + R8A66597_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.name = "r8a66597_hcd",
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.start = 2,
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.end = 2,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device r8a66597_usb_host_device = {
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.name = "r8a66597_hcd",
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.id = -1,
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.dev = {
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.dma_mask = NULL,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
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.resource = r8a66597_usb_host_resources,
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};
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static struct resource sm501_resources[] = {
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[0] = {
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.start = SM107_MEM_ADDR,
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.end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = SM107_REG_ADDR,
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.end = SM107_REG_ADDR + SM107_REG_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[2] = {
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.start = 10,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct fb_videomode sm501_default_mode_crt = {
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.pixclock = 35714, /* 28MHz */
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.xres = 640,
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.yres = 480,
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.left_margin = 105,
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.right_margin = 16,
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.upper_margin = 33,
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.lower_margin = 10,
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.hsync_len = 39,
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.vsync_len = 2,
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.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
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};
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static struct fb_videomode sm501_default_mode_pnl = {
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.pixclock = 40000, /* 25MHz */
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.xres = 640,
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.yres = 480,
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.left_margin = 2,
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.right_margin = 16,
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.upper_margin = 33,
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.lower_margin = 10,
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.hsync_len = 39,
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.vsync_len = 2,
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.sync = 0,
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};
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static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = {
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.def_bpp = 16,
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.def_mode = &sm501_default_mode_pnl,
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.flags = SM501FB_FLAG_USE_INIT_MODE |
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SM501FB_FLAG_USE_HWCURSOR |
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SM501FB_FLAG_USE_HWACCEL |
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SM501FB_FLAG_DISABLE_AT_EXIT |
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SM501FB_FLAG_PANEL_NO_VBIASEN,
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};
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static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = {
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.def_bpp = 16,
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.def_mode = &sm501_default_mode_crt,
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.flags = SM501FB_FLAG_USE_INIT_MODE |
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SM501FB_FLAG_USE_HWCURSOR |
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SM501FB_FLAG_USE_HWACCEL |
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SM501FB_FLAG_DISABLE_AT_EXIT,
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};
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static struct sm501_platdata_fb sm501_fb_pdata = {
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.fb_route = SM501_FB_OWN,
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.fb_crt = &sm501_pdata_fbsub_crt,
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.fb_pnl = &sm501_pdata_fbsub_pnl,
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};
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static struct sm501_initdata sm501_initdata = {
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.gpio_high = {
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.set = 0x00001fe0,
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.mask = 0x0,
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},
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.devices = 0,
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.mclk = 84 * 1000000,
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.m1xclk = 112 * 1000000,
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};
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static struct sm501_platdata sm501_platform_data = {
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.init = &sm501_initdata,
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.fb = &sm501_fb_pdata,
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};
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static struct platform_device sm501_device = {
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.name = "sm501",
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.id = -1,
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.dev = {
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.platform_data = &sm501_platform_data,
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},
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.num_resources = ARRAY_SIZE(sm501_resources),
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.resource = sm501_resources,
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};
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static struct resource i2c_resources[] = {
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[0] = {
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.start = PCA9564_ADDR,
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.end = PCA9564_ADDR + PCA9564_SIZE - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
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},
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[1] = {
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.start = 12,
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.end = 12,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct i2c_pca9564_pf_platform_data i2c_platform_data = {
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.gpio = 0,
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.i2c_clock_speed = I2C_PCA_CON_330kHz,
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.timeout = 100,
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};
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static struct platform_device i2c_device = {
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.name = "i2c-pca-platform",
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.id = -1,
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.dev = {
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.platform_data = &i2c_platform_data,
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},
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.num_resources = ARRAY_SIZE(i2c_resources),
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.resource = i2c_resources,
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};
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static struct platform_device *sh7785lcr_devices[] __initdata = {
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&heartbeat_device,
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&nor_flash_device,
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&r8a66597_usb_host_device,
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&sm501_device,
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&i2c_device,
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};
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static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = {
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{
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I2C_BOARD_INFO("r2025sd", 0x32),
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},
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};
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static int __init sh7785lcr_devices_setup(void)
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{
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i2c_register_board_info(0, sh7785lcr_i2c_devices,
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ARRAY_SIZE(sh7785lcr_i2c_devices));
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return platform_add_devices(sh7785lcr_devices,
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ARRAY_SIZE(sh7785lcr_devices));
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}
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__initcall(sh7785lcr_devices_setup);
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/* Initialize IRQ setting */
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void __init init_sh7785lcr_IRQ(void)
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{
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plat_irq_setup_pins(IRQ_MODE_IRQ7654);
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plat_irq_setup_pins(IRQ_MODE_IRQ3210);
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}
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static void sh7785lcr_power_off(void)
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{
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ctrl_outb(0x01, P2SEGADDR(PLD_POFCR));
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}
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/* Initialize the board */
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static void __init sh7785lcr_setup(char **cmdline_p)
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{
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void __iomem *sm501_reg;
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printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n");
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pm_power_off = sh7785lcr_power_off;
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/* sm501 DRAM configuration */
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sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL;
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writel(0x000307c2, sm501_reg);
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}
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/*
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* The Machine Vector
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*/
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static struct sh_machine_vector mv_sh7785lcr __initmv = {
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.mv_name = "SH7785LCR",
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.mv_setup = sh7785lcr_setup,
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.mv_init_irq = init_sh7785lcr_IRQ,
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};
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File diff suppressed because it is too large
Load Diff
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@ -23,3 +23,4 @@ obj-$(CONFIG_SH_LANDISK) += ops-landisk.o
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obj-$(CONFIG_SH_LBOX_RE2) += ops-lboxre2.o fixups-lboxre2.o
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obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += ops-se7780.o fixups-se7780.o
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obj-$(CONFIG_SH_CAYMAN) += ops-cayman.o
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obj-$(CONFIG_SH_SH7785LCR) += ops-sh7785lcr.o fixups-sh7785lcr.o
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@ -0,0 +1,46 @@
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/*
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* arch/sh/drivers/pci/fixups-sh7785lcr.c
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*
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* R0P7785LC0011RL PCI fixups
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* Copyright (C) 2008 Yoshihiro Shimoda
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*
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* Based on arch/sh/drivers/pci/fixups-r7780rp.c
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* Copyright (C) 2003 Lineo uSolutions, Inc.
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* Copyright (C) 2004 - 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/pci.h>
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#include "pci-sh4.h"
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int pci_fixup_pcic(void)
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{
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pci_write_reg(0x000043ff, SH4_PCIINTM);
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pci_write_reg(0x0000380f, SH4_PCIAINTM);
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pci_write_reg(0xfbb00047, SH7780_PCICMD);
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pci_write_reg(0x00000000, SH7780_PCIIBAR);
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pci_write_reg(0x00011912, SH7780_PCISVID);
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pci_write_reg(0x08000000, SH7780_PCICSCR0);
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pci_write_reg(0x0000001b, SH7780_PCICSAR0);
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pci_write_reg(0xfd000000, SH7780_PCICSCR1);
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pci_write_reg(0x0000000f, SH7780_PCICSAR1);
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pci_write_reg(0xfd000000, SH7780_PCIMBR0);
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pci_write_reg(0x00fc0000, SH7780_PCIMBMR0);
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#ifdef CONFIG_32BIT
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pci_write_reg(0xc0000000, SH7780_PCIMBR2);
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pci_write_reg(0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
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#endif
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/* Set IOBR for windows containing area specified in pci.h */
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pci_write_reg((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)),
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SH7780_PCIIOBR);
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pci_write_reg(((SH7780_PCI_IO_SIZE - 1) & (7 << 18)), SH7780_PCIIOBMR);
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return 0;
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}
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@ -0,0 +1,66 @@
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/*
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* Author: Ian DaSilva (idasilva@mvista.com)
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*
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* Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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* PCI initialization for the Renesas R0P7785LC0011RL board
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* Based on arch/sh/drivers/pci/ops-r7780rp.c
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*
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include "pci-sh4.h"
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static char irq_tab[] __initdata = {
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65, 66, 67, 68,
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};
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int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
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{
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return irq_tab[slot];
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}
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static struct resource sh7785_io_resource = {
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.name = "SH7785_IO",
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.start = SH7780_PCI_IO_BASE,
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.end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO
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};
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static struct resource sh7785_mem_resource = {
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.name = "SH7785_mem",
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.start = SH7780_PCI_MEMORY_BASE,
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.end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM
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};
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struct pci_channel board_pci_channels[] = {
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{ &sh4_pci_ops, &sh7785_io_resource, &sh7785_mem_resource, 0, 0xff },
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{ NULL, NULL, NULL, 0, 0 },
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};
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EXPORT_SYMBOL(board_pci_channels);
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static struct sh4_pci_address_map sh7785_pci_map = {
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.window0 = {
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.base = SH7780_CS2_BASE_ADDR,
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.size = 0x04000000,
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},
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.window1 = {
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.base = SH7780_CS3_BASE_ADDR,
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.size = 0x04000000,
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},
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.flags = SH4_PCIC_NO_RESET,
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};
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int __init pcibios_init_platform(void)
|
||||
{
|
||||
return sh7780_pcic_init(&sh7785_pci_map);
|
||||
}
|
||||
|
|
@ -49,3 +49,4 @@ MIGOR SH_MIGOR
|
|||
RSK7203 SH_RSK7203
|
||||
AP325RXA SH_AP325RXA
|
||||
SH7763RDP SH_SH7763RDP
|
||||
SH7785LCR SH_SH7785LCR
|
||||
|
|
|
|||
|
|
@ -0,0 +1,55 @@
|
|||
#ifndef __ASM_SH_RENESAS_SH7785LCR_H
|
||||
#define __ASM_SH_RENESAS_SH7785LCR_H
|
||||
|
||||
/*
|
||||
* This board has 2 physical memory maps.
|
||||
* It can be changed with DIP switch(S2-5).
|
||||
*
|
||||
* phys address | S2-5 = OFF | S2-5 = ON
|
||||
* -----------------------------+---------------+---------------
|
||||
* 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
|
||||
* 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
|
||||
* 0x06000000 - 0x07ffffff(CS1) | reserved | I2C
|
||||
* 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
|
||||
* 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
|
||||
* 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
|
||||
* 0x14000000 - 0x17ffffff(CS5) | I2C | USB
|
||||
* 0x18000000 - 0x1bffffff(CS6) | reserved | SD
|
||||
* 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
|
||||
*
|
||||
*/
|
||||
|
||||
#define NOR_FLASH_ADDR 0x00000000
|
||||
#define NOR_FLASH_SIZE 0x04000000
|
||||
|
||||
#define PLD_BASE_ADDR 0x04000000
|
||||
#define PLD_PCICR (PLD_BASE_ADDR + 0x00)
|
||||
#define PLD_LCD_BK_CONTR (PLD_BASE_ADDR + 0x02)
|
||||
#define PLD_LOCALCR (PLD_BASE_ADDR + 0x04)
|
||||
#define PLD_POFCR (PLD_BASE_ADDR + 0x06)
|
||||
#define PLD_LEDCR (PLD_BASE_ADDR + 0x08)
|
||||
#define PLD_SWSR (PLD_BASE_ADDR + 0x0a)
|
||||
#define PLD_VERSR (PLD_BASE_ADDR + 0x0c)
|
||||
#define PLD_MMSR (PLD_BASE_ADDR + 0x0e)
|
||||
|
||||
#define SM107_MEM_ADDR 0x10000000
|
||||
#define SM107_MEM_SIZE 0x00e00000
|
||||
#define SM107_REG_ADDR 0x13e00000
|
||||
#define SM107_REG_SIZE 0x00200000
|
||||
|
||||
#if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS)
|
||||
#define R8A66597_ADDR 0x14000000 /* USB */
|
||||
#define CG200_ADDR 0x18000000 /* SD */
|
||||
#define PCA9564_ADDR 0x06000000 /* I2C */
|
||||
#else
|
||||
#define R8A66597_ADDR 0x08000000
|
||||
#define CG200_ADDR 0x0c000000
|
||||
#define PCA9564_ADDR 0x14000000
|
||||
#endif
|
||||
|
||||
#define R8A66597_SIZE 0x00000100
|
||||
#define CG200_SIZE 0x00010000
|
||||
#define PCA9564_SIZE 0x00000100
|
||||
|
||||
#endif /* __ASM_SH_RENESAS_SH7785LCR_H */
|
||||
|
||||
Loading…
Reference in New Issue