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net: dsa: mv88e6xxx: prefix Port Control 1 macros

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For implicit namespacing and clarity, prefix the common Port Control 1
Register macros with MV88E6XXX_PORT_CTL1.

Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vivien Didelot 2017-06-12 12:37:38 -04:00 committed by David S. Miller
parent a89b433bee
commit cd985bbf9a
2 changed files with 15 additions and 10 deletions
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17
drivers/net/dsa/mv88e6xxx/port.c
View File

@ -595,16 +595,16 @@ int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
u16 val; u16 val;
int err; int err;
err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, &val); err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
if (err) if (err)
return err; return err;
if (message_port) if (message_port)
val |= PORT_CONTROL_1_MESSAGE_PORT; val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
else else
val &= ~PORT_CONTROL_1_MESSAGE_PORT; val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
return mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, val); return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
} }
/* Offset 0x06: Port Based VLAN Map */ /* Offset 0x06: Port Based VLAN Map */
@ -646,7 +646,8 @@ int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
/* Port's default FID upper bits are located in reg 0x05, offset 0 */ /* Port's default FID upper bits are located in reg 0x05, offset 0 */
if (upper_mask) { if (upper_mask) {
err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, &reg); err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
&reg);
if (err) if (err)
return err; return err;
@ -679,14 +680,16 @@ int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
/* Port's default FID upper bits are located in reg 0x05, offset 0 */ /* Port's default FID upper bits are located in reg 0x05, offset 0 */
if (upper_mask) { if (upper_mask) {
err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, &reg); err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
&reg);
if (err) if (err)
return err; return err;
reg &= ~upper_mask; reg &= ~upper_mask;
reg |= (fid >> 4) & upper_mask; reg |= (fid >> 4) & upper_mask;
err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg); err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1,
reg);
if (err) if (err)
return err; return err;
} }

8
drivers/net/dsa/mv88e6xxx/port.h
View File

@ -141,9 +141,11 @@
#define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002 #define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002
#define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003 #define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003
#define PORT_CONTROL_1 0x05 /* Offset 0x05: Port Control 1 */
#define PORT_CONTROL_1_MESSAGE_PORT BIT(15) #define MV88E6XXX_PORT_CTL1 0x05
#define PORT_CONTROL_1_FID_11_4_MASK (0xff << 0) #define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000
#define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff
#define PORT_BASE_VLAN 0x06 #define PORT_BASE_VLAN 0x06
#define PORT_BASE_VLAN_FID_3_0_MASK (0xf << 12) #define PORT_BASE_VLAN_FID_3_0_MASK (0xf << 12)
#define PORT_DEFAULT_VLAN 0x07 #define PORT_DEFAULT_VLAN 0x07