clk: qcom: rcg2: Add support for display port clock ops
New display port clock ops supported for display port clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/20190731182713.8123-2-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -14,6 +14,7 @@ menuconfig COMMON_CLK_QCOM
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tristate "Support for Qualcomm's clock controllers"
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depends on OF
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depends on ARCH_QCOM || COMPILE_TEST
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select RATIONAL
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select REGMAP_MMIO
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select RESET_CONTROLLER
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@ -161,6 +161,7 @@ extern const struct clk_ops clk_byte2_ops;
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extern const struct clk_ops clk_pixel_ops;
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extern const struct clk_ops clk_gfx3d_ops;
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extern const struct clk_ops clk_rcg2_shared_ops;
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extern const struct clk_ops clk_dp_ops;
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struct clk_rcg_dfs_data {
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struct clk_rcg2 *rcg;
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@ -10,6 +10,7 @@
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#include <linux/export.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/rational.h>
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#include <linux/regmap.h>
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#include <linux/math64.h>
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#include <linux/slab.h>
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@ -1124,3 +1125,79 @@ int qcom_cc_register_rcg_dfs(struct regmap *regmap,
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return 0;
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}
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EXPORT_SYMBOL_GPL(qcom_cc_register_rcg_dfs);
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static int clk_rcg2_dp_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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struct freq_tbl f = { 0 };
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u32 mask = BIT(rcg->hid_width) - 1;
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u32 hid_div, cfg;
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int i, num_parents = clk_hw_get_num_parents(hw);
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unsigned long num, den;
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rational_best_approximation(parent_rate, rate,
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GENMASK(rcg->mnd_width - 1, 0),
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GENMASK(rcg->mnd_width - 1, 0), &den, &num);
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if (!num || !den)
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return -EINVAL;
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regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
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hid_div = cfg;
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cfg &= CFG_SRC_SEL_MASK;
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cfg >>= CFG_SRC_SEL_SHIFT;
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for (i = 0; i < num_parents; i++) {
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if (cfg == rcg->parent_map[i].cfg) {
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f.src = rcg->parent_map[i].src;
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break;
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}
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}
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f.pre_div = hid_div;
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f.pre_div >>= CFG_SRC_DIV_SHIFT;
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f.pre_div &= mask;
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if (num != den) {
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f.m = num;
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f.n = den;
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} else {
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f.m = 0;
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f.n = 0;
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}
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return clk_rcg2_configure(rcg, &f);
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}
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static int clk_rcg2_dp_set_rate_and_parent(struct clk_hw *hw,
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unsigned long rate, unsigned long parent_rate, u8 index)
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{
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return clk_rcg2_dp_set_rate(hw, rate, parent_rate);
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}
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static int clk_rcg2_dp_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_rate_request parent_req = *req;
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int ret;
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ret = __clk_determine_rate(clk_hw_get_parent(hw), &parent_req);
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if (ret)
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return ret;
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req->best_parent_rate = parent_req.rate;
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return 0;
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}
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const struct clk_ops clk_dp_ops = {
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.is_enabled = clk_rcg2_is_enabled,
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.get_parent = clk_rcg2_get_parent,
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.set_parent = clk_rcg2_set_parent,
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.recalc_rate = clk_rcg2_recalc_rate,
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.set_rate = clk_rcg2_dp_set_rate,
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.set_rate_and_parent = clk_rcg2_dp_set_rate_and_parent,
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.determine_rate = clk_rcg2_dp_determine_rate,
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};
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EXPORT_SYMBOL_GPL(clk_dp_ops);
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