clk: add table lookup to mux
Add a table lookup feature to the mux clock. Also allow arbitrary masks instead of the width. This will be used by some clocks on Tegra114. Also adapt the tegra periph clk because it uses struct clk_mux directly. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Peter De Schrijver
Mike Turquette
parent
5fda6858a4
commit
ce4f3313b0
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@ -32,6 +32,7 @@
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static u8 clk_mux_get_parent(struct clk_hw *hw)
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{
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struct clk_mux *mux = to_clk_mux(hw);
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int num_parents = __clk_get_num_parents(hw->clk);
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u32 val;
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/*
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@ -42,7 +43,16 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
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* val = 0x4 really means "bit 2, index starts at bit 0"
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*/
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val = readl(mux->reg) >> mux->shift;
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val &= (1 << mux->width) - 1;
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val &= mux->mask;
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if (mux->table) {
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int i;
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for (i = 0; i < num_parents; i++)
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if (mux->table[i] == val)
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return i;
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return -EINVAL;
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}
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if (val && (mux->flags & CLK_MUX_INDEX_BIT))
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val = ffs(val) - 1;
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@ -50,7 +60,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
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if (val && (mux->flags & CLK_MUX_INDEX_ONE))
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val--;
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if (val >= __clk_get_num_parents(hw->clk))
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if (val >= num_parents)
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return -EINVAL;
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return val;
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@ -62,17 +72,22 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
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u32 val;
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unsigned long flags = 0;
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if (mux->flags & CLK_MUX_INDEX_BIT)
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index = (1 << ffs(index));
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if (mux->table)
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index = mux->table[index];
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if (mux->flags & CLK_MUX_INDEX_ONE)
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index++;
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else {
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if (mux->flags & CLK_MUX_INDEX_BIT)
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index = (1 << ffs(index));
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if (mux->flags & CLK_MUX_INDEX_ONE)
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index++;
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}
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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val = readl(mux->reg);
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val &= ~(((1 << mux->width) - 1) << mux->shift);
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val &= ~(mux->mask << mux->shift);
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val |= index << mux->shift;
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writel(val, mux->reg);
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@ -88,10 +103,10 @@ const struct clk_ops clk_mux_ops = {
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};
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EXPORT_SYMBOL_GPL(clk_mux_ops);
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struct clk *clk_register_mux(struct device *dev, const char *name,
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struct clk *clk_register_mux_table(struct device *dev, const char *name,
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const char **parent_names, u8 num_parents, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_mux_flags, spinlock_t *lock)
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void __iomem *reg, u8 shift, u32 mask,
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u8 clk_mux_flags, u32 *table, spinlock_t *lock)
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{
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struct clk_mux *mux;
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struct clk *clk;
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@ -113,9 +128,10 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
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/* struct clk_mux assignments */
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mux->reg = reg;
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mux->shift = shift;
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mux->width = width;
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mux->mask = mask;
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mux->flags = clk_mux_flags;
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mux->lock = lock;
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mux->table = table;
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mux->hw.init = &init;
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clk = clk_register(dev, &mux->hw);
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@ -125,3 +141,15 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
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return clk;
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}
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struct clk *clk_register_mux(struct device *dev, const char *name,
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const char **parent_names, u8 num_parents, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_mux_flags, spinlock_t *lock)
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{
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u32 mask = BIT(width) - 1;
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return clk_register_mux_table(dev, name, parent_names, num_parents,
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flags, reg, shift, mask, clk_mux_flags,
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NULL, lock);
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}
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@ -355,15 +355,16 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
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struct tegra_clk_periph *periph, void __iomem *clk_base,
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u32 offset);
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#define TEGRA_CLK_PERIPH(_mux_shift, _mux_width, _mux_flags, \
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#define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \
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_div_shift, _div_width, _div_frac_width, \
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_div_flags, _clk_num, _enb_refcnt, _regs, \
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_gate_flags) \
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_gate_flags, _table) \
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{ \
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.mux = { \
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.flags = _mux_flags, \
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.shift = _mux_shift, \
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.width = _mux_width, \
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.mask = _mux_mask, \
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.table = _table, \
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}, \
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.divider = { \
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.flags = _div_flags, \
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@ -393,26 +394,36 @@ struct tegra_periph_init_data {
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const char *dev_id;
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};
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#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset, \
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_mux_shift, _mux_width, _mux_flags, _div_shift, \
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#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
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_mux_shift, _mux_mask, _mux_flags, _div_shift, \
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_div_width, _div_frac_width, _div_flags, _regs, \
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_clk_num, _enb_refcnt, _gate_flags, _clk_id) \
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_clk_num, _enb_refcnt, _gate_flags, _clk_id, _table) \
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{ \
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.name = _name, \
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.clk_id = _clk_id, \
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.parent_names = _parent_names, \
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.num_parents = ARRAY_SIZE(_parent_names), \
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.periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_width, \
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.periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \
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_mux_flags, _div_shift, \
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_div_width, _div_frac_width, \
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_div_flags, _clk_num, \
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_enb_refcnt, _regs, \
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_gate_flags), \
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_gate_flags, _table), \
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.offset = _offset, \
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.con_id = _con_id, \
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.dev_id = _dev_id, \
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}
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#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
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_mux_shift, _mux_width, _mux_flags, _div_shift, \
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_div_width, _div_frac_width, _div_flags, _regs, \
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_clk_num, _enb_refcnt, _gate_flags, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
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_mux_shift, BIT(_mux_width) - 1, _mux_flags, \
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_div_shift, _div_width, _div_frac_width, _div_flags, \
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_regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\
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NULL)
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/**
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* struct clk_super_mux - super clock
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*
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@ -152,7 +152,7 @@ struct clk {
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}, \
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.reg = _reg, \
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.shift = _shift, \
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.width = _width, \
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.mask = BIT(_width) - 1, \
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.flags = _mux_flags, \
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.lock = _lock, \
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}; \
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@ -297,8 +297,9 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
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struct clk_mux {
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struct clk_hw hw;
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void __iomem *reg;
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u32 *table;
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u32 mask;
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u8 shift;
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u8 width;
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u8 flags;
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spinlock_t *lock;
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};
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@ -307,11 +308,17 @@ struct clk_mux {
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#define CLK_MUX_INDEX_BIT BIT(1)
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extern const struct clk_ops clk_mux_ops;
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struct clk *clk_register_mux(struct device *dev, const char *name,
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const char **parent_names, u8 num_parents, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_mux_flags, spinlock_t *lock);
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struct clk *clk_register_mux_table(struct device *dev, const char *name,
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const char **parent_names, u8 num_parents, unsigned long flags,
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void __iomem *reg, u8 shift, u32 mask,
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u8 clk_mux_flags, u32 *table, spinlock_t *lock);
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/**
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* struct clk_fixed_factor - fixed multiplier and divider clock
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*
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