MIPS: Netlogic: Update comments in smpboot.S
No change in logic, comments update and whitespace cleanup. * A few comments in the file were in assembler style and the rest int C style, convert all of them to C style. * Mark workarounds for Ax silicon with a macro XLP_AX_WORKAROUND * Whitespace fixes - use tabs consistently * rename __config_lsu macro to xlp_config_lsu Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3749/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Jayachandran C
Ralf Baechle
parent
28a33cbc24
commit
cedc8ef87c
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@ -54,28 +54,36 @@
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XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
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SYS_CPU_NONCOHERENT_MODE * 4
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.macro __config_lsu
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li t0, LSU_DEFEATURE
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mfcr t1, t0
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#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */
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lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */
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or t1, t1, t2
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li t2, ~0xe /* S1RCM */
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/* Enable XLP features and workarounds in the LSU */
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.macro xlp_config_lsu
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li t0, LSU_DEFEATURE
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mfcr t1, t0
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lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */
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or t1, t1, t2
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#ifdef XLP_AX_WORKAROUND
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li t2, ~0xe /* S1RCM */
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and t1, t1, t2
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#endif
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mtcr t1, t0
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li t0, SCHED_DEFEATURE
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lui t1, 0x0100 /* Experimental: Disable BRU accepting ALU ops */
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mtcr t1, t0
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#ifdef XLP_AX_WORKAROUND
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li t0, SCHED_DEFEATURE
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lui t1, 0x0100 /* Disable BRU accepting ALU ops */
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mtcr t1, t0
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#endif
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.endm
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/*
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* The cores can come start when they are woken up. This is also the NMI
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* entry, so check that first.
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* This is the code that will be copied to the reset entry point for
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* XLR and XLP. The XLP cores start here when they are woken up. This
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* is also the NMI entry point.
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*
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* The data corresponding to reset is stored at RESET_DATA_PHYS location,
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* this will have the thread mask (used when core is woken up) and the
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* current NMI handler in case we reached here for an NMI.
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* The data corresponding to reset/NMI is stored at RESET_DATA_PHYS
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* location, this will have the thread mask (used when core is woken up)
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* and the current NMI handler in case we reached here for an NMI.
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*
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* When a core or thread is newly woken up, it loops in a 'wait'. When
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* the CPU really needs waking up, we send an NMI to it, with the NMI
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@ -89,12 +97,12 @@
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FEXPORT(nlm_reset_entry)
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dmtc0 k0, $22, 6
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dmtc0 k1, $22, 7
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mfc0 k0, CP0_STATUS
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li k1, 0x80000
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and k1, k0, k1
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beqz k1, 1f /* go to real reset entry */
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mfc0 k0, CP0_STATUS
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li k1, 0x80000
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and k1, k0, k1
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beqz k1, 1f /* go to real reset entry */
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nop
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li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
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li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
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ld k0, BOOT_NMI_HANDLER(k1)
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jr k0
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nop
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@ -114,21 +122,23 @@ FEXPORT(nlm_reset_entry)
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li t2, SYS_CPU_COHERENT_BASE(0)
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add t2, t2, t3 /* t2 <- SYS offset for node */
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lw t1, 0(t2)
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and t1, t1, t0
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sw t1, 0(t2)
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and t1, t1, t0
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sw t1, 0(t2)
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/* read back to ensure complete */
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lw t1, 0(t2)
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lw t1, 0(t2)
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sync
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/* Configure LSU on Non-0 Cores. */
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__config_lsu
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xlp_config_lsu
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/* FALL THROUGH */
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/*
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* Wake up sibling threads from the initial thread in
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* a core.
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*/
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EXPORT(nlm_boot_siblings)
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/* Enable hw threads by writing to MAP_THREADMODE of the core */
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li t0, CKSEG1ADDR(RESET_DATA_PHYS)
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lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
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li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
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@ -139,13 +149,14 @@ EXPORT(nlm_boot_siblings)
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/*
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* The new hardware thread starts at the next instruction
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* For all the cases other than core 0 thread 0, we will
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* jump to the secondary wait function.
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*/
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* jump to the secondary wait function.
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*/
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mfc0 v0, CP0_EBASE, 1
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andi v0, 0x7f /* v0 <- node/core */
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#if 1
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/* A0 errata - Write MMU_SETUP after changing thread mode register. */
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/* Init MMU in the first thread after changing THREAD_MODE
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* register (Ax Errata?)
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*/
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andi v1, v0, 0x3 /* v1 <- thread id */
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bnez v1, 2f
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nop
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@ -154,9 +165,8 @@ EXPORT(nlm_boot_siblings)
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li t1, 0
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mtcr t1, t0
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ehb
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#endif
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2: beqz v0, 4f
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2: beqz v0, 4f /* boot cpu (cpuid == 0)? */
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nop
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/* setup status reg */
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@ -183,9 +193,9 @@ EXPORT(nlm_boot_siblings)
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* For the boot CPU, we have to restore registers and
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* return
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*/
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4: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
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4: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
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li t1, 0xfadebeef
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dmtc0 t1, $4, 2 /* restore SP from UserLocal */
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dmtc0 t1, $4, 2 /* restore SP from UserLocal */
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PTR_SUBU sp, t0, PT_SIZE
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RESTORE_ALL
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jr ra
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@ -193,7 +203,7 @@ EXPORT(nlm_boot_siblings)
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EXPORT(nlm_reset_entry_end)
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FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
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__config_lsu
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xlp_config_lsu
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dmtc0 sp, $4, 2 /* SP saved in UserLocal */
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SAVE_ALL
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sync
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@ -234,36 +244,36 @@ END(nlm_boot_secondary_cpus)
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*/
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__CPUINIT
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NESTED(nlm_rmiboot_preboot, 16, sp)
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mfc0 t0, $15, 1 # read ebase
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andi t0, 0x1f # t0 has the processor_id()
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andi t2, t0, 0x3 # thread no
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sll t0, 2 # offset in cpu array
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mfc0 t0, $15, 1 /* read ebase */
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andi t0, 0x1f /* t0 has the processor_id() */
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andi t2, t0, 0x3 /* thread num */
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sll t0, 2 /* offset in cpu array */
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PTR_LA t1, nlm_cpu_ready # mark CPU ready
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PTR_LA t1, nlm_cpu_ready /* mark CPU ready */
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PTR_ADDU t1, t0
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li t3, 1
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sw t3, 0(t1)
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bnez t2, 1f # skip thread programming
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nop # for non zero hw threads
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bnez t2, 1f /* skip thread programming */
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nop /* for thread id != 0 */
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/*
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* MMU setup only for first thread in core
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* XLR MMU setup only for first thread in core
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*/
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li t0, 0x400
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mfcr t1, t0
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li t2, 6 # XLR thread mode mask
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li t2, 6 /* XLR thread mode mask */
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nor t3, t2, zero
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and t2, t1, t2 # t2 - current thread mode
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and t2, t1, t2 /* t2 - current thread mode */
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li v0, CKSEG1ADDR(RESET_DATA_PHYS)
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lw v1, BOOT_THREAD_MODE(v0) # v1 - new thread mode
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lw v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
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sll v1, 1
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beq v1, t2, 1f # same as request value
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nop # nothing to do */
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beq v1, t2, 1f /* same as request value */
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nop /* nothing to do */
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and t2, t1, t3 # mask out old thread mode
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or t1, t2, v1 # put in new value
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mtcr t1, t0 # update core control
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and t2, t1, t3 /* mask out old thread mode */
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or t1, t2, v1 /* put in new value */
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mtcr t1, t0 /* update core control */
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1: wait
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j 1b
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