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perf/core improvements and fixes: 

report/script/trace/top:
 
   Arnaldo Carvalho de Melo:
 
   - Allow specifying marker events demarcating when to consider the other events,
     i.e. one now can state something like:
 
         # perf probe kernel_function
         # perf record -e cycles,probe:kernel_function
 
     And then, in 'perf script' or 'perf report' say:
 
         # perf report --switch-on=probe:kernel_function
 
     And then the cycles event samples will be considered only after we
     find the first probe:kernel_function event.
 
     There is also --switch-off=event, to make it stop considering events
     out of some window, say to avoid some winding down of a workload.
 
     The same can be done with the "live mode" tools: 'perf top' and 'perf trace'.
 
     There are examples in the cset comments showing how to use it with
     SDT events in things like 'systemtap', that have those tracepoint-like
     events for the start/end of passes, etc.
 
     Another example involves selecting scheduler events + entry/exit of
     a syscall, using the syscalls tracepoints, one can then see the
     scheduler events that take place while that syscall is being processed.
 
     In the future this should be possible in record/top/trace via eBPF
     where the perf tools would hook into the marker events and enable events
     put in place but not enabled when the on/off conditions are the desired
     ones, reducing the amount of events sampled, but this userspace only
     solution should be good enough for many scenarios.
 
 perf vendor events intel:
 
   Haiyan Song:
 
   - Add Tremontx event file v1.02.
 
 unwind:
 
   John Keeping:
 
   - Fix callchain unwinding when tid != pid, that was working only for the
     thread group leader.
 
 Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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 commit e2736219e6
 Author: John Keeping <john@metanate.com>
 Date:   Thu Aug 15 11:01:46 2019 +0100
 
     perf unwind: Remove unnecessary test
 
     If dwarf_callchain_users is false, then unwind__prepare_access() will
     not set unwind_libunwind_ops so the remaining test here is sufficient.
 
     Signed-off-by: John Keeping <john@metanate.com>
     Reviewed-by: Jiri Olsa <jolsa@kernel.org>
     Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
     Cc: Konstantin Khlebnikov <khlebnikov@yandex-team.ru>
     Cc: Namhyung Kim <namhyung@kernel.org>
     Cc: Peter Zijlstra <peterz@infradead.org>
     Cc: john keeping <john@metanate.com>
     Link: http://lkml.kernel.org/r/20190815100146.28842-3-john@metanate.com
     Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
 
 diff --git a/tools/perf/util/unwind-libunwind.c b/tools/perf/util/unwind-libunwind.c
 index b843f9d0a9ea..6499b22b158b 100644
 --- a/tools/perf/util/unwind-libunwind.c
 +++ b/tools/perf/util/unwind-libunwind.c
 @@ -69,18 +69,12 @@ int unwind__prepare_access(struct map_groups *mg, struct map *map,
 
  void unwind__flush_access(struct map_groups *mg)
  {
 -	if (!dwarf_callchain_users)
 -		return;
 -
  	if (mg->unwind_libunwind_ops)
  		mg->unwind_libunwind_ops->flush_access(mg);
  }
 
  void unwind__finish_access(struct map_groups *mg)
  {
 -	if (!dwarf_callchain_users)
 -		return;
 -
  	if (mg->unwind_libunwind_ops)
  		mg->unwind_libunwind_ops->finish_access(mg);
  }
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Merge tag 'perf-core-for-mingo-5.4-20190816' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core

Pull perf/core improvements and fixes from Arnaldo:

report/script/trace/top:

  Arnaldo Carvalho de Melo:

  - Allow specifying marker events demarcating when to consider the other events,
    i.e. one now can state something like:

        # perf probe kernel_function
        # perf record -e cycles,probe:kernel_function

    And then, in 'perf script' or 'perf report' say:

        # perf report --switch-on=probe:kernel_function

    And then the cycles event samples will be considered only after we
    find the first probe:kernel_function event.

    There is also --switch-off=event, to make it stop considering events
    out of some window, say to avoid some winding down of a workload.

    The same can be done with the "live mode" tools: 'perf top' and 'perf trace'.

    There are examples in the cset comments showing how to use it with
    SDT events in things like 'systemtap', that have those tracepoint-like
    events for the start/end of passes, etc.

    Another example involves selecting scheduler events + entry/exit of
    a syscall, using the syscalls tracepoints, one can then see the
    scheduler events that take place while that syscall is being processed.

    In the future this should be possible in record/top/trace via eBPF
    where the perf tools would hook into the marker events and enable events
    put in place but not enabled when the on/off conditions are the desired
    ones, reducing the amount of events sampled, but this userspace only
    solution should be good enough for many scenarios.

perf vendor events intel:

  Haiyan Song:

  - Add Tremontx event file v1.02.

unwind:

  John Keeping:

  - Fix callchain unwinding when tid != pid, that was working only for the
    thread group leader.

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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=IaYE
-----END PGP SIGNATURE-----

commit e2736219e6
Author: John Keeping <john@metanate.com>
Date:   Thu Aug 15 11:01:46 2019 +0100

    perf unwind: Remove unnecessary test

    If dwarf_callchain_users is false, then unwind__prepare_access() will
    not set unwind_libunwind_ops so the remaining test here is sufficient.

    Signed-off-by: John Keeping <john@metanate.com>
    Reviewed-by: Jiri Olsa <jolsa@kernel.org>
    Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
    Cc: Konstantin Khlebnikov <khlebnikov@yandex-team.ru>
    Cc: Namhyung Kim <namhyung@kernel.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: john keeping <john@metanate.com>
    Link: http://lkml.kernel.org/r/20190815100146.28842-3-john@metanate.com
    Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

diff --git a/tools/perf/util/unwind-libunwind.c b/tools/perf/util/unwind-libunwind.c
index b843f9d0a9ea..6499b22b158b 100644
--- a/tools/perf/util/unwind-libunwind.c
+++ b/tools/perf/util/unwind-libunwind.c
@@ -69,18 +69,12 @@ int unwind__prepare_access(struct map_groups *mg, struct map *map,

 void unwind__flush_access(struct map_groups *mg)
 {
-	if (!dwarf_callchain_users)
-		return;
-
 	if (mg->unwind_libunwind_ops)
 		mg->unwind_libunwind_ops->flush_access(mg);
 }

 void unwind__finish_access(struct map_groups *mg)
 {
-	if (!dwarf_callchain_users)
-		return;
-
 	if (mg->unwind_libunwind_ops)
 		mg->unwind_libunwind_ops->finish_access(mg);
 }
This commit is contained in:
Thomas Gleixner 2019-08-16 22:43:42 +02:00
parent 4511708b9a e2736219e6
commit cfb104ca8a
29 changed files with 1158 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
tools/perf/Documentation/perf-report.txt
View File

@ -438,6 +438,23 @@ OPTIONS
perf report --time 0%-10%,30%-40%
--switch-on EVENT_NAME::
Only consider events after this event is found.
This may be interesting to measure a workload only after some initialization
phase is over, i.e. insert a perf probe at that point and then using this
option with that probe.
--switch-off EVENT_NAME::
Stop considering events after this event is found.
--show-on-off-events::
Show the --switch-on/off events too. This has no effect in 'perf report' now
but probably we'll make the default not to show the switch-on/off events
on the --group mode and if there is only one event besides the off/on ones,
go straight to the histogram browser, just like 'perf report' with no events
explicitely specified does.
--itrace::
Options for decoding instruction tracing data. The options are:

9
tools/perf/Documentation/perf-script.txt
View File

@ -417,6 +417,15 @@ include::itrace.txt[]
For itrace only show specified functions and their callees for
itrace. Multiple functions can be separated by comma.
--switch-on EVENT_NAME::
Only consider events after this event is found.
--switch-off EVENT_NAME::
Stop considering events after this event is found.
--show-on-off-events::
Show the --switch-on/off events too.
SEE ALSO
--------
linkperf:perf-record[1], linkperf:perf-script-perl[1],

38
tools/perf/Documentation/perf-top.txt
View File

@ -266,6 +266,44 @@ Default is to monitor all CPUS.
Record events of type PERF_RECORD_NAMESPACES and display it with the
'cgroup_id' sort key.
--switch-on EVENT_NAME::
Only consider events after this event is found.
E.g.:
Find out where broadcast packets are handled
perf probe -L icmp_rcv
Insert a probe there:
perf probe icmp_rcv:59
Start perf top and ask it to only consider the cycles events when a
broadcast packet arrives This will show a menu with two entries and
will start counting when a broadcast packet arrives:
perf top -e cycles,probe:icmp_rcv --switch-on=probe:icmp_rcv
Alternatively one can ask for --group and then two overhead columns
will appear, the first for cycles and the second for the switch-on event.
perf top --group -e cycles,probe:icmp_rcv --switch-on=probe:icmp_rcv
This may be interesting to measure a workload only after some initialization
phase is over, i.e. insert a perf probe at that point and use the above
examples replacing probe:icmp_rcv with the just-after-init probe.
--switch-off EVENT_NAME::
Stop considering events after this event is found.
--show-on-off-events::
Show the --switch-on/off events too. This has no effect in 'perf top' now
but probably we'll make the default not to show the switch-on/off events
on the --group mode and if there is only one event besides the off/on ones,
go straight to the histogram browser, just like 'perf top' with no events
explicitely specified does.
INTERACTIVE PROMPTING KEYS
--------------------------

9
tools/perf/Documentation/perf-trace.txt
View File

@ -176,6 +176,15 @@ the thread executes on the designated CPUs. Default is to monitor all CPUs.
only at exit time or when a syscall is interrupted, i.e. in those cases this
option is equivalent to the number of lines printed.
--switch-on EVENT_NAME::
Only consider events after this event is found.
--switch-off EVENT_NAME::
Stop considering events after this event is found.
--show-on-off-events::
Show the --switch-on/off events too.
--max-stack::
Set the stack depth limit when parsing the callchain, anything
beyond the specified depth will be ignored. Note that at this point

10
tools/perf/builtin-report.c
View File

@ -25,6 +25,7 @@
#include "util/debug.h"
#include "util/evlist.h"
#include "util/evsel.h"
#include "util/evswitch.h"
#include "util/header.h"
#include "util/session.h"
#include "util/tool.h"
@ -60,6 +61,7 @@
struct report {
struct perf_tool tool;
struct perf_session *session;
struct evswitch evswitch;
bool use_tui, use_gtk, use_stdio;
bool show_full_info;
bool show_threads;
@ -243,6 +245,9 @@ static int process_sample_event(struct perf_tool *tool,
return 0;
}
if (evswitch__discard(&rep->evswitch, evsel))
return 0;
if (machine__resolve(machine, &al, sample) < 0) {
pr_debug("problem processing %d event, skipping it.\n",
event->header.type);
@ -1189,6 +1194,7 @@ int cmd_report(int argc, const char **argv)
OPT_CALLBACK(0, "time-quantum", &symbol_conf.time_quantum, "time (ms|us|ns|s)",
"Set time quantum for time sort key (default 100ms)",
parse_time_quantum),
OPTS_EVSWITCH(&report.evswitch),
OPT_END()
};
struct perf_data data = {
@ -1257,6 +1263,10 @@ repeat:
if (session == NULL)
return -1;
ret = evswitch__init(&report.evswitch, session->evlist, stderr);
if (ret)
return ret;
if (zstd_init(&(session->zstd_data), 0) < 0)
pr_warning("Decompression initialization failed. Reported data may be incomplete.\n");

10
tools/perf/builtin-script.c
View File

@ -16,6 +16,7 @@
#include "util/trace-event.h"
#include "util/evlist.h"
#include "util/evsel.h"
#include "util/evswitch.h"
#include "util/sort.h"
#include "util/data.h"
#include "util/auxtrace.h"
@ -1628,6 +1629,7 @@ struct perf_script {
bool show_bpf_events;
bool allocated;
bool per_event_dump;
struct evswitch evswitch;
struct perf_cpu_map *cpus;
struct perf_thread_map *threads;
int name_width;
@ -1805,6 +1807,9 @@ static void process_event(struct perf_script *script,
if (!show_event(sample, evsel, thread, al))
return;
if (evswitch__discard(&script->evswitch, evsel))
return;
++es->samples;
perf_sample__fprintf_start(sample, thread, evsel,
@ -3538,6 +3543,7 @@ int cmd_script(int argc, const char **argv)
"file", "file saving guest os /proc/kallsyms"),
OPT_STRING(0, "guestmodules", &symbol_conf.default_guest_modules,
"file", "file saving guest os /proc/modules"),
OPTS_EVSWITCH(&script.evswitch),
OPT_END()
};
const char * const script_subcommands[] = { "record", "report", NULL };
@ -3862,6 +3868,10 @@ int cmd_script(int argc, const char **argv)
script.range_num);
}
err = evswitch__init(&script.evswitch, session->evlist, stderr);
if (err)
goto out_delete;
err = __cmd_script(&script);
flush_scripting();

10
tools/perf/builtin-top.c
View File

@ -1148,8 +1148,11 @@ static int deliver_event(struct ordered_events *qe,
evsel = perf_evlist__id2evsel(session->evlist, sample.id);
assert(evsel != NULL);
if (event->header.type == PERF_RECORD_SAMPLE)
if (event->header.type == PERF_RECORD_SAMPLE) {
if (evswitch__discard(&top->evswitch, evsel))
return 0;
++top->samples;
}
switch (sample.cpumode) {
case PERF_RECORD_MISC_USER:
@ -1534,6 +1537,7 @@ int cmd_top(int argc, const char **argv)
"number of thread to run event synthesize"),
OPT_BOOLEAN(0, "namespaces", &opts->record_namespaces,
"Record namespaces events"),
OPTS_EVSWITCH(&top.evswitch),
OPT_END()
};
struct evlist *sb_evlist = NULL;
@ -1567,6 +1571,10 @@ int cmd_top(int argc, const char **argv)
goto out_delete_evlist;
}
status = evswitch__init(&top.evswitch, top.evlist, stderr);
if (status)
goto out_delete_evlist;
if (symbol_conf.report_hierarchy) {
/* disable incompatible options */
symbol_conf.event_group = false;

10
tools/perf/builtin-trace.c
View File

@ -27,6 +27,7 @@
#include "util/env.h"
#include "util/event.h"
#include "util/evlist.h"
#include "util/evswitch.h"
#include <subcmd/exec-cmd.h>
#include "util/machine.h"
#include "util/map.h"
@ -106,6 +107,7 @@ struct trace {
unsigned long nr_events;
unsigned long nr_events_printed;
unsigned long max_events;
struct evswitch evswitch;
struct strlist *ev_qualifier;
struct {
size_t nr;
@ -2680,6 +2682,9 @@ static void trace__handle_event(struct trace *trace, union perf_event *event, st
return;
}
if (evswitch__discard(&trace->evswitch, evsel))
return;
trace__set_base_time(trace, evsel, sample);
if (evsel->core.attr.type == PERF_TYPE_TRACEPOINT &&
@ -4157,6 +4162,7 @@ int cmd_trace(int argc, const char **argv)
OPT_UINTEGER('D', "delay", &trace.opts.initial_delay,
"ms to wait before starting measurement after program "
"start"),
OPTS_EVSWITCH(&trace.evswitch),
OPT_END()
};
bool __maybe_unused max_stack_user_set = true;
@ -4380,6 +4386,10 @@ init_augmented_syscall_tp:
}
}
err = evswitch__init(&trace.evswitch, trace.evlist, stderr);
if (err)
goto out_close;
err = target__validate(&trace.opts.target);
if (err) {
target__strerror(&trace.opts.target, err, bf, sizeof(bf));

1
tools/perf/pmu-events/arch/x86/mapfile.csv
View File

@ -35,4 +35,5 @@ GenuineIntel-6-55-[01234],v1,skylakex,core
GenuineIntel-6-55-[56789ABCDEF],v1,cascadelakex,core
GenuineIntel-6-7D,v1,icelake,core
GenuineIntel-6-7E,v1,icelake,core
GenuineIntel-6-86,v1,tremontx,core
AuthenticAMD-23-[[:xdigit:]]+,v1,amdfam17h,core

1 Family-model Version Filename EventType
35 GenuineIntel-6-55-[56789ABCDEF] v1 cascadelakex core
36 GenuineIntel-6-7D v1 icelake core
37 GenuineIntel-6-7E v1 icelake core
38 GenuineIntel-6-86 v1 tremontx core
39 AuthenticAMD-23-[[:xdigit:]]+ v1 amdfam17h core

111
tools/perf/pmu-events/arch/x86/tremontx/cache.json Normal file
View File

@ -0,0 +1,111 @@
[
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts cacheable memory requests that miss in the the Last Level Cache. Requests include Demand Loads, Reads for Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2.",
"EventCode": "0x2e",
"Counter": "0,1,2,3",
"UMask": "0x41",
"PEBScounters": "0,1,2,3",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PDIR_COUNTER": "na",
"SampleAfterValue": "200003",
"BriefDescription": "Counts memory requests originating from the core that miss in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts cacheable memory requests that access the Last Level Cache. Requests include Demand Loads, Reads for Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2.",
"EventCode": "0x2e",
"Counter": "0,1,2,3",
"UMask": "0x4f",
"PEBScounters": "0,1,2,3",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PDIR_COUNTER": "na",
"SampleAfterValue": "200003",
"BriefDescription": "Counts memory requests originating from the core that reference a cache line in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2."
},
{
"PEBS": "1",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of load uops retired. This event is Precise Event capable",
"EventCode": "0xd0",
"Counter": "0,1,2,3",
"UMask": "0x81",
"PEBScounters": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of load uops retired.",
"Data_LA": "1"
},
{
"PEBS": "1",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of store uops retired. This event is Precise Event capable",
"EventCode": "0xd0",
"Counter": "0,1,2,3",
"UMask": "0x82",
"PEBScounters": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of store uops retired.",
"Data_LA": "1"
},
{
"PEBS": "1",
"CollectPEBSRecord": "2",
"EventCode": "0xd1",
"Counter": "0,1,2,3",
"UMask": "0x1",
"PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of load uops retired that hit the level 1 data cache",
"Data_LA": "1"
},
{
"PEBS": "1",
"CollectPEBSRecord": "2",
"EventCode": "0xd1",
"Counter": "0,1,2,3",
"UMask": "0x2",
"PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of load uops retired that hit in the level 2 cache",
"Data_LA": "1"
},
{
"PEBS": "1",
"CollectPEBSRecord": "2",
"EventCode": "0xd1",
"Counter": "0,1,2,3",
"UMask": "0x4",
"PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of load uops retired that miss in the level 3 cache"
},
{
"PEBS": "1",
"CollectPEBSRecord": "2",
"EventCode": "0xd1",
"Counter": "0,1,2,3",
"UMask": "0x8",
"PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of load uops retired that miss in the level 1 data cache",
"Data_LA": "1"
},
{
"PEBS": "1",
"CollectPEBSRecord": "2",
"EventCode": "0xd1",
"Counter": "0,1,2,3",
"UMask": "0x10",
"PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of load uops retired that miss in the level 2 cache",
"Data_LA": "1"
}
]

26
tools/perf/pmu-events/arch/x86/tremontx/frontend.json Normal file
View File

@ -0,0 +1,26 @@
[
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache.",
"EventCode": "0x80",
"Counter": "0,1,2,3",
"UMask": "0x2",
"PEBScounters": "0,1,2,3",
"EventName": "ICACHE.MISSES",
"PDIR_COUNTER": "na",
"SampleAfterValue": "200003",
"BriefDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in a cache line and they do not hit in the ICache (miss)."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.",
"EventCode": "0x80",
"Counter": "0,1,2,3",
"UMask": "0x3",
"PEBScounters": "0,1,2,3",
"EventName": "ICACHE.ACCESSES",
"PDIR_COUNTER": "na",
"SampleAfterValue": "200003",
"BriefDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes cache Line."
}
]

26
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[
{
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0XB7",
"MSRValue": "0x000000003F04000001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts demand data reads that was not supplied by the L3 cache.",
"Offcore": "1"
},
{
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0XB7",
"MSRValue": "0x000000003F04000002",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all demand reads for ownership (RFO) requests and software based prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.",
"Offcore": "1"
}
]

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[
{
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0XB7",
"MSRValue": "0x000000000000010001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts demand data reads that have any response type.",
"Offcore": "1"
},
{
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0XB7",
"MSRValue": "0x000000000000010002",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all demand reads for ownership (RFO) requests and software based prefetches for exclusive ownership (PREFETCHW) that have any response type.",
"Offcore": "1"
}
]

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[
{
"PEBS": "1",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of instructions that retire. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.",
"Counter": "32",
"UMask": "0x1",
"PEBScounters": "32",
"EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of instructions retired. (Fixed event)"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
"Counter": "33",
"UMask": "0x2",
"PEBScounters": "33",
"EventName": "CPU_CLK_UNHALTED.CORE",
"PDIR_COUNTER": "na",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time. This event is not affected by core frequency changes and at a fixed frequency. This event uses fixed counter 2.",
"Counter": "34",
"UMask": "0x3",
"PEBScounters": "34",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PDIR_COUNTER": "na",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.",
"EventCode": "0x3c",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
"PDIR_COUNTER": "na",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of unhalted core clock cycles."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts reference cycles (at TSC frequency) when core is not halted. This event uses a programmable general purpose perfmon counter.",
"EventCode": "0x3c",
"Counter": "0,1,2,3",
"UMask": "0x1",
"PEBScounters": "0,1,2,3",
"EventName": "CPU_CLK_UNHALTED.REF",
"PDIR_COUNTER": "na",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency."
},
{
"PEBS": "1",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a Programmable general purpose perfmon counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event.",
"EventCode": "0xc0",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"EventName": "INST_RETIRED.ANY_P",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of instructions retired."
},
{
"CollectPEBSRecord": "2",
"EventCode": "0xc3",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"EventName": "MACHINE_CLEARS.ANY",
"PDIR_COUNTER": "na",
"SampleAfterValue": "20003",
"BriefDescription": "Counts all machine clears due to, but not limited to memory ordering, memory disambiguation, SMC, page faults and FP assist."
},
{
"PEBS": "1",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event.",
"EventCode": "0xc4",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of branch instructions retired for all branch types."
},
{
"PEBS": "1",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts mispredicted branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event.",
"EventCode": "0xc5",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted branch instructions retired."
},
{
"CollectPEBSRecord": "2",
"EventCode": "0xcd",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"EventName": "CYCLES_DIV_BUSY.ANY",
"PDIR_COUNTER": "na",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts cycles the floating point divider or integer divider or both are busy. Does not imply a stall waiting for either divider."
}
]

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tools/perf/pmu-events/arch/x86/tremontx/uncore-memory.json Normal file
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[
{
"BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x04",
"EventName": "LLC_MISSES.MEM_READ",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x0f",
"Unit": "iMC"
},
{
"BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x04",
"EventName": "LLC_MISSES.MEM_WRITE",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x30",
"Unit": "iMC"
},
{
"BriefDescription": "Memory controller clock ticks",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Pre-charge for reads",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x02",
"EventName": "UNC_M_PRE_COUNT.RD",
"PerPkg": "1",
"UMask": "0x04",
"Unit": "iMC"
},
{
"BriefDescription": "Pre-charge for writes",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x02",
"EventName": "UNC_M_PRE_COUNT.WR",
"PerPkg": "1",
"UMask": "0x08",
"Unit": "iMC"
},
{
"BriefDescription": "Precharge due to read on page miss, write on page miss or PGT",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x02",
"EventName": "UNC_M_PRE_COUNT.ALL",
"PerPkg": "1",
"UMask": "0x1c",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge commands. : Precharge due to page table",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x02",
"EventName": "UNC_M_PRE_COUNT.PGT",
"PerPkg": "1",
"PublicDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel.",
"UMask": "0x10",
"Unit": "iMC"
}
]

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tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json Normal file
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[
{
"BriefDescription": "Uncore cache clock ticks",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventName": "UNC_CHA_CLOCKTICKS",
"PerPkg": "1",
"Unit": "CHA"
},
{
"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x35",
"EventName": "LLC_MISSES.UNCACHEABLE",
"Filter": "config1=0x40e33",
"PerPkg": "1",
"UMask": "0xC001FE01",
"UMaskExt": "0xC001FE",
"Unit": "CHA"
},
{
"BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x35",
"EventName": "LLC_MISSES.MMIO_READ",
"Filter": "config1=0x40040e33",
"PerPkg": "1",
"UMask": "0xC001FE01",
"UMaskExt": "0xC001FE",
"Unit": "CHA"
},
{
"BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x35",
"EventName": "LLC_MISSES.MMIO_WRITE",
"Filter": "config1=0x40041e33",
"PerPkg": "1",
"UMask": "0xC001FE01",
"UMaskExt": "0xC001FE",
"Unit": "CHA"
},
{
"BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x35",
"EventName": "LLC_REFERENCES.STREAMING_FULL",
"Filter": "config1=0x41833",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0xC001FE01",
"UMaskExt": "0xC001FE",
"Unit": "CHA"
},
{
"BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x35",
"EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
"Filter": "config1=0x41a33",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0xC001FE01",
"UMaskExt": "0xC001FE",
"Unit": "CHA"
},
{
"BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0",
"Counter": "0,1",
"CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "LLC_MISSES.PCIE_READ",
"FCMask": "0x07",
"Filter": "ch_mask=0x1f",
"MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
"MetricName": "LLC_MISSES.PCIE_READ",
"PerPkg": "1",
"PortMask": "0x01",
"ScaleUnit": "4Bytes",
"UMask": "0x04",
"Unit": "IIO"
},
{
"BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",
"Counter": "0,1",
"CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "LLC_MISSES.PCIE_WRITE",
"FCMask": "0x07",
"Filter": "ch_mask=0x1f",
"MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
"MetricName": "LLC_MISSES.PCIE_WRITE",
"PerPkg": "1",
"PortMask": "0x01",
"ScaleUnit": "4Bytes",
"UMask": "0x01",
"Unit": "IIO"
},
{
"BriefDescription": "PCI Express bandwidth writing at IIO, part 1",
"Counter": "0,1",
"CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
"ScaleUnit": "4Bytes",
"UMask": "0x01",
"Unit": "IIO"
},
{
"BriefDescription": "PCI Express bandwidth writing at IIO, part 2",
"Counter": "0,1",
"CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
"ScaleUnit": "4Bytes",
"UMask": "0x01",
"Unit": "IIO"
},
{
"BriefDescription": "PCI Express bandwidth writing at IIO, part 3",
"Counter": "0,1",
"CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
"ScaleUnit": "4Bytes",
"UMask": "0x01",
"Unit": "IIO"
},
{
"BriefDescription": "PCI Express bandwidth reading at IIO, part 1",
"Counter": "0,1",
"CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
"ScaleUnit": "4Bytes",
"UMask": "0x04",
"Unit": "IIO"
},
{
"BriefDescription": "PCI Express bandwidth reading at IIO, part 2",
"Counter": "0,1",
"CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
"ScaleUnit": "4Bytes",
"UMask": "0x04",
"Unit": "IIO"
},
{
"BriefDescription": "PCI Express bandwidth reading at IIO, part 3",
"Counter": "0,1",
"CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
"ScaleUnit": "4Bytes",
"UMask": "0x04",
"Unit": "IIO"
},
{
"BriefDescription": "TOR Inserts; CRd misses from local IA",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Code read from local IA that misses in the snoop filter",
"UMask": "0xC80FFE01",
"UMaskExt": "0xC80FFE",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; CRd Pref misses from local IA",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter",
"UMask": "0xC88FFE01",
"UMaskExt": "0xC88FFE",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; DRd Opt misses from local IA",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read opt from local IA that misses in the snoop filter",
"UMask": "0xC827FE01",
"UMaskExt": "0xC827FE",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; DRd Opt Pref misses from local IA",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter",
"UMask": "0xC8A7FE01",
"UMaskExt": "0xC8A7FE",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; RFO misses from local IA",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter",
"UMask": "0xC807FE01",
"UMaskExt": "0xC807FE",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; RFO pref misses from local IA",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter",
"UMask": "0xC887FE01",
"UMaskExt": "0xC887FE",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; WCiL misses from local IA",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
"UMask": "0xC86FFE01",
"UMaskExt": "0xC86FFE",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; WCiLF misses from local IA",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
"UMask": "0xC867FE01",
"UMaskExt": "0xC867FE",
"Unit": "CHA"
},
{
"BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x01",
"EventName": "UNC_IIO_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Clockticks of the integrated IO (IIO) traffic controller",
"Unit": "IIO"
},
{
"BriefDescription": "Data requested of the CPU : Card reading from DRAM",
"Counter": "0,1",
"CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
"PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
"UMask": "0x04",
"Unit": "IIO"
},
{
"BriefDescription": "Data requested of the CPU : Card reading from DRAM",
"Counter": "0,1",
"CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
"PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
"UMask": "0x04",
"Unit": "IIO"
},
{
"BriefDescription": "Data requested of the CPU : Card reading from DRAM",
"Counter": "0,1",
"CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
"PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
"UMask": "0x04",
"Unit": "IIO"
},
{
"BriefDescription": "Data requested of the CPU : Card reading from DRAM",
"Counter": "0,1",
"CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
"PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
"UMask": "0x04",
"Unit": "IIO"
},
{
"BriefDescription": "Data requested of the CPU : Card writing to DRAM",
"Counter": "0,1",
"CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
"PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
"UMask": "0x01",
"Unit": "IIO"
},
{
"BriefDescription": "Data requested of the CPU : Card writing to DRAM",
"Counter": "0,1",
"CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
"PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
"UMask": "0x01",
"Unit": "IIO"
},
{
"BriefDescription": "Data requested of the CPU : Card writing to DRAM",
"Counter": "0,1",
"CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
"PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
"UMask": "0x01",
"Unit": "IIO"
},
{
"BriefDescription": "Data requested of the CPU : Card writing to DRAM",
"Counter": "0,1",
"CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
"PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
"UMask": "0x01",
"Unit": "IIO"
},
{
"BriefDescription": "Clockticks of the IO coherency tracker (IRP)",
"Counter": "0,1",
"CounterType": "PGMABLE",
"EventCode": "0x01",
"EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Clockticks of the IO coherency tracker (IRP)",
"Unit": "IRP"
},
{
"BriefDescription": "Clockticks of the mesh to memory (M2M)",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventName": "UNC_M2M_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Clockticks of the mesh to memory (M2M)",
"Unit": "M2M"
},
{
"BriefDescription": "Clockticks of the mesh to PCI (M2P)",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventCode": "0x01",
"EventName": "UNC_M2P_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Clockticks of the mesh to PCI (M2P)",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
"Counter": "FIXED",
"CounterType": "PGMABLE",
"EventCode": "0xff",
"EventName": "UNC_U_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
"Unit": "UBOX"
}
]

11
tools/perf/pmu-events/arch/x86/tremontx/uncore-power.json Normal file
View File

@ -0,0 +1,11 @@
[
{
"BriefDescription": "Clockticks of the power control unit (PCU)",
"Counter": "0,1,2,3",
"CounterType": "PGMABLE",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Clockticks of the power control unit (PCU)",
"Unit": "PCU"
}
]

86
tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json Normal file
View File

@ -0,0 +1,86 @@
[
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages. The page walks can end with or without a page fault.",
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x2",
"PEBScounters": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PDIR_COUNTER": "na",
"SampleAfterValue": "200003",
"BriefDescription": "Page walk completed due to a demand load to a 4K page."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.",
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x4",
"PEBScounters": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PDIR_COUNTER": "na",
"SampleAfterValue": "200003",
"BriefDescription": "Page walk completed due to a demand load to a 2M or 4M page."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.",
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x2",
"PEBScounters": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PDIR_COUNTER": "na",
"SampleAfterValue": "2000003",
"BriefDescription": "Page walk completed due to a demand data store to a 4K page."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.",
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x4",
"PEBScounters": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PDIR_COUNTER": "na",
"SampleAfterValue": "2000003",
"BriefDescription": "Page walk completed due to a demand data store to a 2M or 4M page."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
"EventCode": "0x81",
"Counter": "0,1,2,3",
"UMask": "0x4",
"PEBScounters": "0,1,2,3",
"EventName": "ITLB.FILLS",
"PDIR_COUNTER": "na",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.",
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x2",
"PEBScounters": "0,1,2,3",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PDIR_COUNTER": "na",
"SampleAfterValue": "2000003",
"BriefDescription": "Page walk completed due to an instruction fetch in a 4K page."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.",
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x4",
"PEBScounters": "0,1,2,3",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PDIR_COUNTER": "na",
"SampleAfterValue": "2000003",
"BriefDescription": "Page walk completed due to an instruction fetch in a 2M or 4M page."
}
]

1
tools/perf/util/Build
View File

@ -9,6 +9,7 @@ perf-y += event.o
perf-y += evlist.o
perf-y += evsel.o
perf-y += evsel_fprintf.o
perf-y += evswitch.o
perf-y += find_bit.o
perf-y += get_current_dir_name.o
perf-y += kallsyms.o

61
tools/perf/util/evswitch.c Normal file
View File

@ -0,0 +1,61 @@
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2019, Red Hat Inc, Arnaldo Carvalho de Melo <acme@redhat.com>
#include "evswitch.h"
#include "evlist.h"
bool evswitch__discard(struct evswitch *evswitch, struct evsel *evsel)
{
if (evswitch->on && evswitch->discarding) {
if (evswitch->on != evsel)
return true;
evswitch->discarding = false;
if (!evswitch->show_on_off_events)
return true;
return false;
}
if (evswitch->off && !evswitch->discarding) {
if (evswitch->off != evsel)
return false;
evswitch->discarding = true;
if (!evswitch->show_on_off_events)
return true;
}
return false;
}
static int evswitch__fprintf_enoent(FILE *fp, const char *evtype, const char *evname)
{
int printed = fprintf(fp, "ERROR: switch-%s event not found (%s)\n", evtype, evname);
return printed += fprintf(fp, "HINT: use 'perf evlist' to see the available event names\n");
}
int evswitch__init(struct evswitch *evswitch, struct evlist *evlist, FILE *fp)
{
if (evswitch->on_name) {
evswitch->on = perf_evlist__find_evsel_by_str(evlist, evswitch->on_name);
if (evswitch->on == NULL) {
evswitch__fprintf_enoent(fp, "on", evswitch->on_name);
return -ENOENT;
}
evswitch->discarding = true;
}
if (evswitch->off_name) {
evswitch->off = perf_evlist__find_evsel_by_str(evlist, evswitch->off_name);
if (evswitch->off == NULL) {
evswitch__fprintf_enoent(fp, "off", evswitch->off_name);
return -ENOENT;
}
}
return 0;
}

31
tools/perf/util/evswitch.h Normal file
View File

@ -0,0 +1,31 @@
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2019, Red Hat Inc, Arnaldo Carvalho de Melo <acme@redhat.com>
#ifndef __PERF_EVSWITCH_H
#define __PERF_EVSWITCH_H 1
#include <stdbool.h>
#include <stdio.h>
struct evsel;
struct evlist;
struct evswitch {
struct evsel *on, *off;
const char *on_name, *off_name;
bool discarding;
bool show_on_off_events;
};
int evswitch__init(struct evswitch *evswitch, struct evlist *evlist, FILE *fp);
bool evswitch__discard(struct evswitch *evswitch, struct evsel *evsel);
#define OPTS_EVSWITCH(evswitch) \
OPT_STRING(0, "switch-on", &(evswitch)->on_name, \
"event", "Consider events after the ocurrence of this event"), \
OPT_STRING(0, "switch-off", &(evswitch)->off_name, \
"event", "Stop considering events after the ocurrence of this event"), \
OPT_BOOLEAN(0, "show-on-off-events", &(evswitch)->show_on_off_events, \
"Show the on/off switch events, used with --switch-on and --switch-off")
#endif /* __PERF_EVSWITCH_H */

5
tools/perf/util/map.c
View File

@ -636,7 +636,7 @@ bool map_groups__empty(struct map_groups *mg)
struct map_groups *map_groups__new(struct machine *machine)
{
struct map_groups *mg = malloc(sizeof(*mg));
struct map_groups *mg = zalloc(sizeof(*mg));
if (mg != NULL)
map_groups__init(mg, machine);
@ -647,6 +647,7 @@ struct map_groups *map_groups__new(struct machine *machine)
void map_groups__delete(struct map_groups *mg)
{
map_groups__exit(mg);
unwind__finish_access(mg);
free(mg);
}
@ -887,7 +888,7 @@ int map_groups__clone(struct thread *thread, struct map_groups *parent)
if (new == NULL)
goto out_unlock;
err = unwind__prepare_access(thread, new, NULL);
err = unwind__prepare_access(mg, new, NULL);
if (err)
goto out_unlock;

4
tools/perf/util/map_groups.h
View File

@ -31,6 +31,10 @@ struct map_groups {
struct maps maps;
struct machine *machine;
refcount_t refcnt;
#ifdef HAVE_LIBUNWIND_SUPPORT
void *addr_space;
struct unwind_libunwind_ops *unwind_libunwind_ops;
#endif
};
#define KMAP_NAME_LEN 256

7
tools/perf/util/thread.c
View File

@ -105,7 +105,6 @@ void thread__delete(struct thread *thread)
}
up_write(&thread->comm_lock);
unwind__finish_access(thread);
nsinfo__zput(thread->nsinfo);
srccode_state_free(&thread->srccode_state);
@ -252,7 +251,7 @@ static int ____thread__set_comm(struct thread *thread, const char *str,
list_add(&new->list, &thread->comm_list);
if (exec)
unwind__flush_access(thread);
unwind__flush_access(thread->mg);
}
thread->comm_set = true;
@ -332,7 +331,7 @@ int thread__insert_map(struct thread *thread, struct map *map)
{
int ret;
ret = unwind__prepare_access(thread, map, NULL);
ret = unwind__prepare_access(thread->mg, map, NULL);
if (ret)
return ret;
@ -352,7 +351,7 @@ static int __thread__prepare_access(struct thread *thread)
down_read(&maps->lock);
for (map = maps__first(maps); map; map = map__next(map)) {
err = unwind__prepare_access(thread, map, &initialized);
err = unwind__prepare_access(thread->mg, map, &initialized);
if (err || initialized)
break;
}

4
tools/perf/util/thread.h
View File

@ -44,10 +44,6 @@ struct thread {
struct thread_stack *ts;
struct nsinfo *nsinfo;
struct srccode_state srccode_state;
#ifdef HAVE_LIBUNWIND_SUPPORT
void *addr_space;
struct unwind_libunwind_ops *unwind_libunwind_ops;
#endif
bool filter;
int filter_entry_depth;
};

2
tools/perf/util/top.h
View File

@ -3,6 +3,7 @@
#define __PERF_TOP_H 1
#include "tool.h"
#include "evswitch.h"
#include "annotate.h"
#include <linux/types.h>
#include <stddef.h>
@ -18,6 +19,7 @@ struct perf_top {
struct evlist *evlist;
struct record_opts record_opts;
struct annotation_options annotation_opts;
struct evswitch evswitch;
/*
* Symbols will be added here in perf_event__process_sample and will
* get out after decayed.

18
tools/perf/util/unwind-libunwind-local.c
View File

@ -616,26 +616,26 @@ static unw_accessors_t accessors = {
.get_proc_name = get_proc_name,
};
static int _unwind__prepare_access(struct thread *thread)
static int _unwind__prepare_access(struct map_groups *mg)
{
thread->addr_space = unw_create_addr_space(&accessors, 0);
if (!thread->addr_space) {
mg->addr_space = unw_create_addr_space(&accessors, 0);
if (!mg->addr_space) {
pr_err("unwind: Can't create unwind address space.\n");
return -ENOMEM;
}
unw_set_caching_policy(thread->addr_space, UNW_CACHE_GLOBAL);
unw_set_caching_policy(mg->addr_space, UNW_CACHE_GLOBAL);
return 0;
}
static void _unwind__flush_access(struct thread *thread)
static void _unwind__flush_access(struct map_groups *mg)
{
unw_flush_cache(thread->addr_space, 0, 0);
unw_flush_cache(mg->addr_space, 0, 0);
}
static void _unwind__finish_access(struct thread *thread)
static void _unwind__finish_access(struct map_groups *mg)
{
unw_destroy_addr_space(thread->addr_space);
unw_destroy_addr_space(mg->addr_space);
}
static int get_entries(struct unwind_info *ui, unwind_entry_cb_t cb,
@ -660,7 +660,7 @@ static int get_entries(struct unwind_info *ui, unwind_entry_cb_t cb,
*/
if (max_stack - 1 > 0) {
WARN_ONCE(!ui->thread, "WARNING: ui->thread is NULL");
addr_space = ui->thread->addr_space;
addr_space = ui->thread->mg->addr_space;
if (addr_space == NULL)
return -1;

40
tools/perf/util/unwind-libunwind.c
View File

@ -11,13 +11,13 @@ struct unwind_libunwind_ops __weak *local_unwind_libunwind_ops;
struct unwind_libunwind_ops __weak *x86_32_unwind_libunwind_ops;
struct unwind_libunwind_ops __weak *arm64_unwind_libunwind_ops;
static void unwind__register_ops(struct thread *thread,
static void unwind__register_ops(struct map_groups *mg,
struct unwind_libunwind_ops *ops)
{
thread->unwind_libunwind_ops = ops;
mg->unwind_libunwind_ops = ops;
}
int unwind__prepare_access(struct thread *thread, struct map *map,
int unwind__prepare_access(struct map_groups *mg, struct map *map,
bool *initialized)
{
const char *arch;
@ -28,7 +28,7 @@ int unwind__prepare_access(struct thread *thread, struct map *map,
if (!dwarf_callchain_users)
return 0;
if (thread->addr_space) {
if (mg->addr_space) {
pr_debug("unwind: thread map already set, dso=%s\n",
map->dso->name);
if (initialized)
@ -37,14 +37,14 @@ int unwind__prepare_access(struct thread *thread, struct map *map,
}
/* env->arch is NULL for live-mode (i.e. perf top) */
if (!thread->mg->machine->env || !thread->mg->machine->env->arch)
if (!mg->machine->env || !mg->machine->env->arch)
goto out_register;
dso_type = dso__type(map->dso, thread->mg->machine);
dso_type = dso__type(map->dso, mg->machine);
if (dso_type == DSO__TYPE_UNKNOWN)
return 0;
arch = perf_env__arch(thread->mg->machine->env);
arch = perf_env__arch(mg->machine->env);
if (!strcmp(arch, "x86")) {
if (dso_type != DSO__TYPE_64BIT)
@ -59,37 +59,31 @@ int unwind__prepare_access(struct thread *thread, struct map *map,
return 0;
}
out_register:
unwind__register_ops(thread, ops);
unwind__register_ops(mg, ops);
err = thread->unwind_libunwind_ops->prepare_access(thread);
err = mg->unwind_libunwind_ops->prepare_access(mg);
if (initialized)
*initialized = err ? false : true;
return err;
}
void unwind__flush_access(struct thread *thread)
void unwind__flush_access(struct map_groups *mg)
{
if (!dwarf_callchain_users)
return;
if (thread->unwind_libunwind_ops)
thread->unwind_libunwind_ops->flush_access(thread);
if (mg->unwind_libunwind_ops)
mg->unwind_libunwind_ops->flush_access(mg);
}
void unwind__finish_access(struct thread *thread)
void unwind__finish_access(struct map_groups *mg)
{
if (!dwarf_callchain_users)
return;
if (thread->unwind_libunwind_ops)
thread->unwind_libunwind_ops->finish_access(thread);
if (mg->unwind_libunwind_ops)
mg->unwind_libunwind_ops->finish_access(mg);
}
int unwind__get_entries(unwind_entry_cb_t cb, void *arg,
struct thread *thread,
struct perf_sample *data, int max_stack)
{
if (thread->unwind_libunwind_ops)
return thread->unwind_libunwind_ops->get_entries(cb, arg, thread, data, max_stack);
if (thread->mg->unwind_libunwind_ops)
return thread->mg->unwind_libunwind_ops->get_entries(cb, arg, thread, data, max_stack);
return 0;
}

25
tools/perf/util/unwind.h
View File

@ -6,6 +6,7 @@
#include <linux/types.h>
struct map;
struct map_groups;
struct perf_sample;
struct symbol;
struct thread;
@ -19,9 +20,9 @@ struct unwind_entry {
typedef int (*unwind_entry_cb_t)(struct unwind_entry *entry, void *arg);
struct unwind_libunwind_ops {
int (*prepare_access)(struct thread *thread);
void (*flush_access)(struct thread *thread);
void (*finish_access)(struct thread *thread);
int (*prepare_access)(struct map_groups *mg);
void (*flush_access)(struct map_groups *mg);
void (*finish_access)(struct map_groups *mg);
int (*get_entries)(unwind_entry_cb_t cb, void *arg,
struct thread *thread,
struct perf_sample *data, int max_stack);
@ -46,20 +47,20 @@ int unwind__get_entries(unwind_entry_cb_t cb, void *arg,
#endif
int LIBUNWIND__ARCH_REG_ID(int regnum);
int unwind__prepare_access(struct thread *thread, struct map *map,
int unwind__prepare_access(struct map_groups *mg, struct map *map,
bool *initialized);
void unwind__flush_access(struct thread *thread);
void unwind__finish_access(struct thread *thread);
void unwind__flush_access(struct map_groups *mg);
void unwind__finish_access(struct map_groups *mg);
#else
static inline int unwind__prepare_access(struct thread *thread __maybe_unused,
static inline int unwind__prepare_access(struct map_groups *mg __maybe_unused,
struct map *map __maybe_unused,
bool *initialized __maybe_unused)
{
return 0;
}
static inline void unwind__flush_access(struct thread *thread __maybe_unused) {}
static inline void unwind__finish_access(struct thread *thread __maybe_unused) {}
static inline void unwind__flush_access(struct map_groups *mg __maybe_unused) {}
static inline void unwind__finish_access(struct map_groups *mg __maybe_unused) {}
#endif
#else
static inline int
@ -72,14 +73,14 @@ unwind__get_entries(unwind_entry_cb_t cb __maybe_unused,
return 0;
}
static inline int unwind__prepare_access(struct thread *thread __maybe_unused,
static inline int unwind__prepare_access(struct map_groups *mg __maybe_unused,
struct map *map __maybe_unused,
bool *initialized __maybe_unused)
{
return 0;
}
static inline void unwind__flush_access(struct thread *thread __maybe_unused) {}
static inline void unwind__finish_access(struct thread *thread __maybe_unused) {}
static inline void unwind__flush_access(struct map_groups *mg __maybe_unused) {}
static inline void unwind__finish_access(struct map_groups *mg __maybe_unused) {}
#endif /* HAVE_DWARF_UNWIND_SUPPORT */
#endif /* __UNWIND_H */