arm64 fixes:
- Fix wrong conflict resolution around CONFIG_ARM64_SSBD - Fix sparse warning on unsigned long constant -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE5RElWfyWxS+3PLO2a9axLQDIXvEFAlv5PPsACgkQa9axLQDI XvGQFhAAjNu9Fmd+++/XhDnWqi9ZgIvC4+2MZhpx9kVZovl7c9cVBLMBIKSkd9Pw d07LlidLa9cKthRmV4Jg+ofckwcbcXq8VO6eMwW1t9Uxm+M9xcJzWaiRFEkOMCTo 5AS0Xh4J/hiZM84NGJuvToT3UpUk/xrMWYzYWg/pUox6VlvjELEdFYiStsuVp4/i wA7qIafX5o3NGRci0nqcBFEDCt46Yrs7TOxpgh/Ybf2jDU+dKw1UBNRQynUos2gl HxxhaAwEfZffBICMhv0noWxxlDoBqtalz86yFeP4ZQlUtl7S2UBPL+XNbecXNCLx SMK7x5cwRqYUiuzUifnEvnSTKcz71dwHAFrYL03dmqjWThzJn5YAYh2ibCy/XMkf excQHF3JGHczkefpDcJcPRmMC3tWXv2A/vpO/EmoOAv+2P9pdFip3tf5qlUSTySi B2hD0MI9hpIvDQCJ7v6TwRc3Y9xXn0zrPmzGHiuwMxiI8O6bGLaZxPu/+I2fgdhk IBKnRArPVfKEGKnG7dZlONr98ayWLZdyD5nOhUyuzHwYSbm8cZiCKq8RUJFfSxAn 6WlL2XI25LqwNZ2OYF0uIkeb3wjLDxYMjt5cegrelLKZAMgVYj6t8X3gk6aR+97O I1OJGBgjPkM81OxLKg67Pc7cmwoQNWgSjGmkRsg4wygkBtylUKg= =2OAx -----END PGP SIGNATURE----- Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fixes from Catalin Marinas:: - Fix wrong conflict resolution around CONFIG_ARM64_SSBD - Fix sparse warning on unsigned long constant * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: cpufeature: Fix mismerge of CONFIG_ARM64_SSBD block arm64: sysreg: fix sparse warnings
This commit is contained in:
commit
d146194f31
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@ -468,7 +468,7 @@
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SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_WXN | \
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SCTLR_ELx_DSSBS | ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0)
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#if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffff
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#if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffffUL
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#error "Inconsistent SCTLR_EL2 set/clear bits"
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#endif
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@ -509,7 +509,7 @@
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SCTLR_EL1_UMA | SCTLR_ELx_WXN | ENDIAN_CLEAR_EL1 |\
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SCTLR_ELx_DSSBS | SCTLR_EL1_NTWI | SCTLR_EL1_RES0)
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#if (SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != 0xffffffffffffffff
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#if (SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != 0xffffffffffffffffUL
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#error "Inconsistent SCTLR_EL1 set/clear bits"
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#endif
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@ -1333,7 +1333,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.cpu_enable = cpu_enable_hw_dbm,
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},
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#endif
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#ifdef CONFIG_ARM64_SSBD
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{
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.desc = "CRC32 instructions",
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.capability = ARM64_HAS_CRC32,
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@ -1343,6 +1342,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.field_pos = ID_AA64ISAR0_CRC32_SHIFT,
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.min_field_value = 1,
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},
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#ifdef CONFIG_ARM64_SSBD
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{
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.desc = "Speculative Store Bypassing Safe (SSBS)",
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.capability = ARM64_SSBS,
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